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document number: mc34844 rev. 9.0, 3/2012 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, inc. , 2009-2012. all rights reserved. 10 channel led backlight driver with integrated power supply the 34844/a is a high efficiency, le d driver for use in backlighting lcd displays from 10" to 20"+. operating from supplies of 7.0 to 28 v, the mc34844/a is capable of driving up to 160 leds in 10 parallel strings. current in the 10 strings is matched to within 2%, and can be programmed via the i 2 c/sm bus interface. the 34844/a also includes a pulse width monitor (pwm) generator for led dimming. the leds can be dimmed to one of 256 levels, programmed through the i 2 c/sm bus interface. up to 65,000:1 (256:1 pwm, 256:1 current dac) dimming ratio. the integrated boost converter generates the minimum output voltage required to keep all leds il luminated with the selected current, providing the highest efficiency possible. the 34844 has an integrated boost self-clocks at a default frequency of 600 khz, but may be programmed via i 2 c to 150/300/ 600/1200 khz. the pwm frequency can be set from 100 hz to 25 khz, or can be synchronized to an external input. if not synchronized to another source, the internal pwm ra te outputs on the ck pin. this enables multiple devices to be synchronized together. the 34844a has a default boost frequency of 320 khz, but may be programmed via i 2 c to 160/320/650/1300 khz. the pwm frequency can be set from 110 hz to 27 khz, or can be synchronized to an external input. if not synchronized to another source, the internal pwm rate outputs on the ck pin. this enables multiple devices to be synchronized together. the 34844/a also supports opt ical/temperature closed loop operation and also features led over-temperature protection, led short protection, and led open circuit protection. the ic also includes over-voltage protection, over-cu rrent protection, and under-voltage lockout. features ? input voltage of 7.0 to 28 v ?2.5 a integrated boost fet ?up to 50 ma on the 34844 led current per channel ?up to 80 ma on the 34844a led current per channel ? 90% efficiency (dc:dc) ?i 2 c/sm bus interface ? 10 channel current mirror with 2% current matching ? boost output voltage up to 60v, wit h dynamic headroom control (dhc) ? pwm frequency programmable or synchronizable from 100 to 25,000 hz for the 34844 ? pwm frequency programmable or synchronizable from 110 to 27,000 hz for the 34844a ? 32-ld 5x5x1.0mm tqfn package applications ? monitors and hdtv - up to 42 inch ? personal computer notebooks ? gps screens ? small screen televisions led driver 34844 34844a ep suffix (pb-free) 98asa10800d 32-pin qfn-ep ordering information device temperature range (t a ) package mc34844ep/r2 -40 c to 105 c 32 qfn-ep mc34844aep/r2
analog integrated circuit device data 2 freescale semiconductor 34844 figure 1. mc34844 simplifi ed application diagram (sm bus mode) figure 2. mc34844a simplified ap plication diagram (manual mode) 7.0 to 28 v fail pgnda 34844 swa swb vout pgndb i0 i1 i2 i3 i4 i5 i6 i7 i8 i9 vcc gnd sck sda a0/sen iset pin nin vin vdc1 vdc2 vdc3 comp slope ck en pwm control unit m/~s vdc1 vdc1 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ vdc1 7.0 to 28v fail pgnda 34844a swa swb vout pgndb i0 i1 i2 i3 i4 i5 i6 i7 i8 i9 vcc gnd sck sda a0/sen iset pin nin vin comp slope ck en pwm control unit m/~s vdc1 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ vdc1 vout vout pwm pwm vdc1 vdc2 vdc3
analog integrated circuit device data freescale semiconductor 3 34844 device variations device variations mc34844 is within the mc34844 specifications pages 4 to 31 , mc34844a is within the mc34844a specifications pages 32 to 54 table 1. key device variations between the mc34844 and mc34844a electrical parameter (1) condition value unit maximum led current 34844 34844a 55 85 ma led channel sink current 34844 34844a riset=5.1 k 0.1% riset=3.48 k 0.1% (typ) 50 80 ma switching frequency 34844 34844a (bst [1:0]=0) (bst [1:0]=1) (bst [1:0]=2) [default] (bst [1:0]=3) (bst [1:0]=0) (bst [1:0]=1)) [default] (bst [1:0]=2) (bst [1:0]=3) (typ) 0.15 0.30 0.60 1.20 0.16 0.32 0.65 1.30 mhz pwm frequency range 34844 34844a this frequency range applies for master mode, slave mode, and manual mode 100 - 25000 110 - 27000 hz notes 1. refer to the respective electrical parameters for specific details
analog integrated circuit device data 4 freescale semiconductor 34844 mc34844 specifications pages 4 to 31 mc34844 mc34844 specifications pages 4 to 31
analog integrated circuit device data 5 freescale semiconductor 34844 internal block diagram mc34844 internal block diagram figure 3. 34844 simplified internal block diagram vin vdc1 comp en ck pwm sck sda iset pin nin swa swb pgnda fail i0 i1 i2 i3 i4 i5 i6 i7 i8 i9 temp/opto loop control current dac ocp/otp/uvlo pwm generator 10 channel ovp boost clock/pll controller 50 ma current mirror v sense gnd a0/sen pgndb ldo vdc3 vdc2 slope i 2 c interface vout m/~s
analog integrated circuit device data freescale semiconductor 6 34844 pin connections mc34844 pin connections figure 4. 34844 pin connections table 2. 34844 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 14 . pin number pin name pin function formal name definition 1 vin power input voltage input supply 2 pgndb power power ground power ground 3 swb input switch node b boost switch connection b 4 swa input switch node a boost switch connection a 5 pgnda power power ground power ground 6 a0/sen input device select address select, device select pin or ovp hw control 7 en input enable enable pin (active high, internal pull-up) 8 - 17 i0-i9 input led channel led string connections 18 fail open drain fault detection fault detected pin (open drain): no failure = low-impedance failure = high-impedance 19 iset passive current set led current setting resistor 20 pin input positive current scale positive input analog current control 21 nin input negative current scale negative input analog current control 22 slope passive boost slope boost slope compensation setting resistor 23 vdc3 output internal regulator 3 decoupling capacitor for internal phase locked loop power 24 ck input/output clock signal clock synchronization pin (input for m/~s = low - internal pull-up, output for m/~s = high) vin pgndb swb swa pgnda a0/sen en io ck vdc3 slope nin pin iset fail i9 vout vdc2 m/~s comp vdc1 sck sda pwm i1 i2 i3 i4 i5 i6 i7 i8 25 32 31 30 29 28 27 26 24 17 18 19 20 21 22 23 1 8 7 6 5 4 3 2 16 9 101112131415 qfn - ep 5.0 mm x 5.0 mm 32 lead ep gnd ep = exposed pad transparent top view
analog integrated circuit device data 7 freescale semiconductor 34844 pin connections mc34844 25 pwm input external pwm external pwm input (internal pull-down) 26 sda bidirectional i 2 c data i 2 c data line 27 sck bidirectional i 2 c clock i 2 c clock line 28 vdc1 output internal regulator 1 decoupling capacitor for internal logic rail 29 comp passive compensation pin boost converter type compensation pin 30 m/~s input master/slave selector selects master mode (1) or slave mode (0) 31 vdc2 output internal regulator 2 decoupling capacitor for internal regulator 32 vout input voltage output boost output voltage sense pin ep gnd - ground ground reference for all internal circuits other than boost fet table 2. 34844 pin definitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 14 . pin number pin name pin function formal name definition
analog integrated circuit device data freescale semiconductor 8 34844 electrical ch aracteristics maximum ratings mc34844 electrical characteristics maximum ratings table 3. maximum ratings all voltages are with respect to ground, unless otherwise noted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings maximum pin voltages a0/sen i0, i1, i2, i3, i4, i5, i6, i7, i8, i9,en (5) vin swa, swb, vout fail, pin, nin, iset, m/~s, ck, pwm v max 7.0 45 30 65 6.0 v maximum led current i max 55 ma esd voltage (2) human body model (hbm) machine model (mm) v esd + 2000 + 200 v thermal ratings ambient temperature range t a -40 to 105 c junction to ambient temperature (3) t ja 32 c/w junction to case temperature (3) t jc 3.5 c/w maximum junction temperature t j 150 c storage temperature range t sto -40 to 150 c peak package reflow temperature during reflow (4) t pprt 260 c power dissipation ta = 25 c ta = 70 c ta = 85 c ta = 105 c 3.9 2.5 2.0 1.4 w notes 2. esd testing is performed in accordance with the human body model (hbm) (aec-q100-2), and the machine model (mm) (aec-q100- 003), r zap = 0 3. per jedec51 standard for multilayer pcb 4. pin soldering temperature limit is for 10 seconds maximum duration. not designed for immersion soldering. exceeding these lim its may cause malfunction or permanent damage to the device. 5. 45 v is the maximum allowable voltage on all led channels in off-state.
analog integrated circuit device data 9 freescale semiconductor 34844 electrical characteristics static and dynamic electrical characteristics mc34844 static and dynamic electrical characteristics table 4. static and dynamic electrical characteristics characteristics noted under conditions v in = 12 v, v out = 42 v, i led = 50 ma, pwm = vdc1, m/~s = vdc1, pin & nin = vdc1, - 40 c t a 105 c, pgnd = 0 v, unless otherwise noted. characteristic symbol min typ max unit supply supply voltage v in 7.0 12 28 v supply current when shutdown mode manual & sm bus: en = low, sck & sda=low i 2 c: en = low, seti 2 c bit = 1, clri 2 c bit = 0 i shutdown - - 2.0 17 - - a supply current when sleep mode sm-bus: en = low, sck & sda= active, seti2c bit = 0, en bit = 0 i 2 c: en = high, seti 2 c bit = 1, clri 2 c bit = 0, en bit = 0 i sleep - 3.0 - ma supply current when operational mode manual: en= high, sck & sda=low, pwm=low sm-bus: en= low, sck & sda=active, en bit= 1, pwm=low i 2 c: en = high, seti 2 c bit = 1, clri 2 c bit = 0, en bit = 1, pwm=low i operational - 10.0 - ma under-voltage lockout v in rising uvlo 5.4 6.0 6.4 v under-voltage hysteresis v in falling uvlo hyst 150 200 250 mv vdc1 voltage (6) c vdc1 = 2.2 f v dc1 2.4 2.5 2.6 v vdc2 voltage (6) c vdc2 = 2.2 f v dc2 5.5 6.0 6.5 v vdc3 voltage (6) c vdc3 = 2.2 f v dc3 2.4 2.5 2.6 v boost output voltage range (7) vin = 7.0 v vin = 28 v v out1 v out2 8.0 31 - - 43 60 v boost switch current limit i fet 2.3 2.5 2.7 a rdson of internal fet i drain = 1.0 a r dson - 250 500 m boost switch off-state leakage current v swa,swb = 65 v i boost_leak - - 10 a peak boost efficiency (8) eff boost - 90 - % notes 6. this output is for internal use only and not to be used for other purposes. a 1.0 k resistor between the vdc3 and vdc1 pin is recommended for <-20 c operation. 7. minimum and maximum output voltages are dependent on min/max duty cycle condition. 8. guaranteed by design
analog integrated circuit device data freescale semiconductor 10 34844 electrical ch aracteristics static and dynamic elec trical characteristics mc34844 line regulation (9) vin=7.0 to 28 v i out /v in -0.2 - 0.2 %/v load regulation (9) vled = 8.0 to 65 v (all channels) i out /v led -0.2 - 0.2 %/v slope compensation voltage ramp r slope = 68 k v slope - 0.49 - v/ s current sense amplifier gain a csa - 9.0 - current sense resistor r sense - 22 - m ota transconductance g m - 200 - s transconductance sink and source current capability i ss - 100 - a output voltage precharge v hold 0.45 0.5 0.55 v fail pin off-state leakage current v fail = 5.5 v i fail_leak - - 5 a on-state voltage drop i sink = 4.0 ma v ol - - 0.4 v led channels sink current ichx register = 255, riset=5.1 k 0.1%, pin&nin = disabled, t a =25 c i sink 49 50 51 ma regulated minimum voltage across drivers pulse width > 4.0 s v min 675 750 825 mv current matching accuracy i match -2.0 - 2.0 % i set pin voltage riset=5.1 k 0.1% v set 2.017 2.048 2.079 v led current amplitude resolution 1.0 ma < i led < 50 ma iled res - 1.5 - % off-state leakage current, all channels (v ch = 45 v) i ch_leak - - 10 a pin input voltage to disable pin mode v pin_dis 2.2 - - v pin bias current pin = v set i pin -2.0 - 2.0 a analog dimming current ichx register = 255, riset=5.1 k 0.1% pin = v set /2 pin = v set i dim_pin 23.75 47.50 25 50 26.25 52.50 ma notes 9. guaranteed by design table 4. static and dynamic elec trical characteristics (continued) characteristics noted under conditions v in = 12 v, v out = 42 v, i led = 50 ma, pwm = vdc1, m/~s = vdc1, pin & nin = vdc1, - 40 c t a 105 c, pgnd = 0 v, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 11 freescale semiconductor 34844 electrical characteristics static and dynamic electrical characteristics mc34844 nin input voltage to disable nin mode v nin_dis 2.2 - - v nin bias current nin = v set i nin -2.0 - 2.0 a analog dimming current ichx register = 255, riset=5.1 k 0.1% nin = v set /2 nin = 0 v i dim_nin 23.75 47.50 25 50 26.25 52.50 ma over-temperature protection over-temperature threshold (10) rising hysteresis o tt 150 - 165 25 175 - c i 2 c/sm bus physical layer [sck, sda] i 2 c address adr i2c - 1110110 - binary sm-bus address adr smb - 1110110 - binary input low voltage v ili -0.3 - 0.8 v input high voltage v ihi 2.1 - 5.5 v input hysteresis v hysi 0.3 - - v output low voltage sink current < 4.0 ma v oli - - 0.4 v input current i ini -5.0 - 5.0 a input capacitance (10) c ini - - 10 f logic inputs / outputs (ck, m/~s, pwm, a0/sen) input low voltage v ill -0.3 - 0.5 v input high voltage v ihl 1.5 - 5.5 v input hysteresis v hysl - 0.1 - v input current i iil -5.0 - 5.0 a output low voltage (ck) i sink < 2.0 ma v oll - - 0.2 v output high voltage (ck) i source < 2.0 ma v ohl 2.2 - 5.5 v input capacitance (10) c ini - - 5.0 f notes 10. guaranteed by design table 4. static and dynamic elect rical characteristics (continued) characteristics noted under conditions v in = 12 v, v out = 42 v, i led = 50 ma, pwm = vdc1, m/~s = vdc1, pin & nin = vdc1, - 40 c t a 105 c, pgnd = 0 v, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 12 34844 electrical ch aracteristics static and dynamic elec trical characteristics mc34844 over-voltage protection over-voltage clamp - ovp register table: ovp = fh ovp fh 60.5 62.5 64.5 v ovp = eh ovp eh 56.5 58 60 v ovp = dh ovp dh 53 54 56 v ovp = ch ovp ch 49 51 52.5 v ovp = bh ovp bh 45 47 48.5 v ovp = ah ovp ah 41 43 44.5 v ovp = 9h ovp 9h 38 39 40.5 v ovp = 8h ovp 8h 34 36 37.5 v ovp = 7h ovp 7h 30.5 32 33.5 v ovp = 6h ovp 6h 26 28 30 v ovp = 5h ovp 5h 23 24 25 v ovp = 4h ovp 4h 19 20 21 v ovp = 3h ovp 3h 15 16 17 v ovp = 2h ovp 2h 11 12 13 v over-voltage threshold, set by hardware, voltage at a0/sen ovp hw 6.15 6.5 6.85 v a0/sen sink current i sink_ovp - 100 - a boost switching frequency (bst [1:0]=0) f sw0 0.14 0.15 0.17 mhz switching frequency (bst [1:0]=1) f sw1 0.27 0.30 0.33 mhz switching frequency (bst [1:0]=2) f sw2 0.54 0.60 0.66 mhz switching frequency (bst [1:0]=3) f sw3 1.08 1.2 1.32 mhz minimum duty cycle d min - 10 15 % maximum duty cycle d max 80 85 - % soft start period t ss - 6.5 - ms boost switch rise time (10) t tr - 15 - ns boost switch fall time (10) t f - 25 - ns notes 11. guaranteed by design table 4. static and dynamic elec trical characteristics (continued) characteristics noted under conditions v in = 12 v, v out = 42 v, i led = 50 ma, pwm = vdc1, m/~s = vdc1, pin & nin = vdc1, - 40 c t a 105 c, pgnd = 0 v, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 13 freescale semiconductor 34844 electrical characteristics static and dynamic electrical characteristics mc34844 pwm generator pwm frequency range (13) m/~s = low (slave mode) fpwm s 100 - 25000 hz pwm frequency m/~s = high (master mode) fpwm register = 768 fpwm register = 192,000 fpwm m 22500 90 25000 100 27500 110 hz pwm dimming resolution t fpwm - 0.39 - % pwm pin (direct pwm control) input pwm pin minimum pulse (13) t pwm_in 150 - - ns input pwm frequency range fpwm 100 - 23000 hz phase lock loop ck slave mode frequency lock range (12) m/~s = low (slave mode) fck s 100 - 25000 hz ck slave mode input jitter (13) m/~s = low (slave mode) fck s_jitter - - 0.1 % slave mode acquisition time m/~s = low (slave mode) fpwm s =25 khz fpwm s =100 hz t s_acq - - - 2000 50 - ms ms ck frequency (master mode) fpwm register = 768 fpwm register = 192,000 fck master 22500 90 25000 100 27500 110 hz i 2 c/sm bus physical layer [sck, sda] interface frequency range f sck 400 khz sm bus power-on-reset time t rst - - 100 ms output fall time 10 f < c l < 400 f t f 40 - 160 ns output rise time 10 f < c l < 400 f t r 20 - 80 ns logic output (ck) output rise and fall time (12) c l < 100 f t r /t f - - 25 ns led channels channels rise and fall time (13) t r /t f - 23 50 ns notes 12. special considerations should be made for frequencies between 100 hz to 1.0 khz. please refer to functional device operation for further details. 13. guaranteed by design table 4. static and dynamic elect rical characteristics (continued) characteristics noted under conditions v in = 12 v, v out = 42 v, i led = 50 ma, pwm = vdc1, m/~s = vdc1, pin & nin = vdc1, - 40 c t a 105 c, pgnd = 0 v, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 14 34844 functional description introduction mc34844 functional description introduction led backlighting has become very popular for small and medium lcds, due to some advantages over other backlighting schemes, such as the widely used cold cathode fluorescent lamp (ccfl). the advantages of led backlighting are low cost, long life, immunity to vibration, low operational voltage, and precise control over its intensity. however, there is an important drawback of this method. it requires more power than most of the other methods, and this is a major problem if the lcd size is large enough. to address the power consumption problem, solid state optoelectronics technologies are evolving to create brighter leds with lower power c onsumption. these new technologies together with highly efficient power management led drivers are turning leds, a more suitable solution for backlighting almost any size of lcd panel, with really conservative power consumption. one of the most common schemes for backlighting with led is the one known as ?array backlighting?. this creates a matrix of leds all over the l cd surface, using defraction and diffused layers to produce an homogenous and even light at the lcd surface. each row or column is formed by a number of leds in series, forcing a single current to flow through all leds in each string. using a current control driver, per row or column, helps the system to maintain a constant current flowing through each line, keeping a steady amount of light even with the presence of line or load variations. they can also be use as a light intensity control by increasing or decreasing the amount of current flowing through each led string. to achieve enough voltage to drive a number of leds in series, a boost converter is implemented, to produce a higher voltage from a smaller one, wh ich is typically used by the logical blocks to do their function. the 34844 implements a single channel boost converter together with 10 input channels, for driving up to 16 leds per string to create a matrix of more than 160 leds. together with its 90% efficiency and i 2 c programmable or external current control, among other features, makes the 34844 a perfect solution for backlighting small and medium size lcd panels, on low power portable and high definition devices. functional pin description input voltage supply (vin) ic power input supply voltage, is used internally to produce internal voltage regulation (vdc1, vdc3) for logic functioning, and also as an input voltage for the boost regulator. internal voltage regulator 1 (vdc1) this pin is for internal use only, and not to be used for other purposes. a capacitor of 2.2 f should be connected between this pin and ground for decoupling purposes. internal voltage regulator 2 (vdc2) this pin is for internal use only, and not to be used for other purposes. a capacitor of 2.2 f should be connected between this pin and ground for decoupling purposes. internal voltage regulator 3 (vdc3) this pin is for internal use only, and not to be used for other purposes. a capacitor of 2.2 f should be connected between this pin and ground for decoupling purposes. a 1.0 k resistor between the vdc3 and vdc1 pin is recommended for <-20 c operation. boost compensation pin (comp) passive pin used to compensat e the boost converter. add a capacitor and a resistor in series to gnd to stabilize the system. ic enable (en) the active high enable pin is internally pulled high through pull-up resistor s. applying 0 v to this pin would stop the ic from working. input/output clock signal (ck) this pin can be used as an output clock signal (master mode), or input clock signal (slave mode), to synchronize more than one device. master/slave mode selection (m/~s) setting this pin high puts the device into master mode, producing an output synchronization clock at the ck pin. setting this pin low, puts the device in slave mode, using the ck pin as an input clock. external pwm input (pwm) this pin is internally pulled down. an external pwm signal can be applied to modulate the led channel directly in absence of an i 2 c interface. clock i 2 c signal (sck) clock line for i 2 c communication. address i 2 c signal (sda) address line for i 2 c communication.
analog integrated circuit device data 15 freescale semiconductor 34844 functional description functional pin description mc34844 a0/sen address select, device select pin, or hardware over- voltage protection (ovp) control. current set (iset) each led string can drive up to 50 ma. the maximum current can be set by using a resistor from this pin to gnd. positive current scaling (pin) positive current scaling factor for the external analog current control. applying 0 v to this pin, scales the current to near 0%, and in the same way, applying 2.048 v (vset), the scale factor is 100%. by applying a voltage higher than 2.2 v, the scaling factor is disabled, and the internal pull-ups are activated. if pin pin and nin pin are used at the same time then by applying 0 v to the pin pin and 2.048 v to nin pin, scales the current to near 0%, and in the same way, applying 2.048 v to the pin pin and 0 v to nin pin, scales the current to 100%. by applying a voltage higher than 2.2 v, the scaling factor is disabled and the internal pull-ups are activated in both pins. negative current scaling (nin) negative current scaling factor for the external analog current control. setting 0 v to this pin scale s the current to 100%, in the same way, setting 2.048 v (vset) the scale factor is near 0%. by applying a voltage higher than 2.2 v, the scaling factor is disabled and the internal pull-ups are activated. if pin pin and nin pin are used at the same time then by applying 0 v to the pin pin and 2.048 v to nin pin, scales the current near 0%, and in the same way, applying 2.048 v to the pin pin and 0 v to nin pin, scales the current to 100%. by applying a voltage higher than 2.2 v, the scaling factor is disabled and the internal pull-ups are activated in both pins. ground (gnd) ground reference for all internal circuits other than the boost fet. the exposed pad (ep) should be used for thermal heat dissipation. i0-i9 current led driver, each line has the capability of driving up to 50 ma. fault detection pin (fail) when a fault situation is detected, this pin goes into high impedance. boost slope compensation setting resistor (slope) use an external resistor of about 68 k to configure the boost compensation slope. power ground pins (pgnda, pgndb) ground pin for the internal boost fet. output voltage sense pin (vout) input pin to monitor the output voltage. it also supplies the input voltage for the internal regulator 2 (vdc2). switching node pins (swa, swb) switching node of boost converter.
analog integrated circuit device data freescale semiconductor 16 34844 functional description functional internal block description mc34844 functional internal block description figure 5. functional internal block diagram regulators/ power down the 34844 is designed to operate from input voltages in the 7.0 to 28 v range. this is stepped down internally by ldos to 2.5 v (vdc1 and vdc3) and 6 v (vdc3) for powering internal circuitry. if the input voltage falls below the uvlo threshold, the device au tomatically enters in power down mode. operating modes: the device can be operated by the en pin and/or sda/ sck bus lines, resulting in three distinct operation modes: ? manual mode, there is no i 2 c capability, the bus line pins must be tied low, and the en pin controls the on/off operation. ? sm bus mode, en pin must be tied low and the device is turned on by any activity on the bus lines. the part shuts down if the bus lines are held low for more than 27 ms, the 27 ms watchdog timer can be disabled by i 2 c (setting seti2c bit high) or tying the en pin high. in sleep mode (en bit=0) the device reduces the power consumption by leaving ?alive? only the blocks required for i 2 c communication. ?i 2 c mode, has to be configured by i 2 c communication (seti2c bit = 1) right after the ic is turned on, it prevents the part from being turned on/off by the bus. sleep mode is also present and it is intended to save power, but still keep the ic prepared to communicate by i 2 c. turning the en pin off, the chip enters into a low power mode. mc34844 - functional block diagram regulator / power down protection / failure detection led channels led channels logic control regulators / power down 3 internal regulators protection / failure detection logic control serial interface control boost boost optical and temperature control pwm dimming over-temperature protection led open protection over-current protection under-voltage protection over-voltage protection
analog integrated circuit device data 17 freescale semiconductor 34844 functional description functional internal block description mc34844 boost the integrated boost converter operates in non- synchronous mode and integrates a 2.5 a fet. an integrated sense circuit is used to sense the voltage at the led current mirror inputs and automatically sets the boost output voltage (dhc) to the minimum voltage needed to keep all leds biased with the required current. the dhc is designed to operate under specific pulse wid th conditions in the led drivers. it operates for pulse widths higher than 4.0 s if the pulse widths are shor ter than specified, the dhc circuit will not operate and the voltage across the led drivers will increase to a value given by the ovp minus the total led voltage in the led stri ng. therefore it is im perative to select the proper ovp level to minimize power dissipation. the ovp can be set from 11 to 62 v, ~4.0 v spaced, using the i 2 c interface (ovp register). if i 2 c capability is not present, the ovp can be controlled by a resistor divider connected from vout to gnd with its mid point tied to a0/ sen pin (threshold = 6.5 v). during an ovp condition, the output voltage will go to the ovp level which is programmed via the i 2 c interface or settled by a resistor divider on a0/sen pin, or by a zener diode. the formulas to calculate the hardware ovp using any of the two methods are as follows: hardware ovp : the ovp value should be set to greater than the maximum led voltage over the whole temperature range. a good practice is to set it 5.0 v or so above the max led voltage. the boost converter also features internal over-current protection (ocp) and has a user programmable over- voltage protection (ovp). the ocp operates on a cycle by cycle basis. however, if the ocp condition remains for more than 10 ms then the device turns off the led drivers, the boost goes to sleep mode and the output fault pin goes into high-impedance. the device can only be restarte d by recycling the enable or creating a power on reset (por). the user can program the boost frequency by i 2 c (bst[1:0]) only after the ic is powered up and before the boost circuit is turned on for the first time (pwm pin low to high). this sequence avoids boost frequency to be changed inadvertently during o peration. the first i 2 c command has to wait for 5.0 ms after the part is turned on, in order to allow sufficient time for the device power up sequence to be completed. the boost controller has an integral track and hold amplifier with indefinite hold time capability, to enable immediate led on cycl es after extended off times. during extended off times, the external leds cool down from their normal quiescent operating temperature and thereby experience a forward voltage chan ge, typically an increase in the forward voltage. this change can be significant for applications with a large number of series leds in a string operating at high current. if the boost controller did not track this increased change, the pote ntial on the led drivers would saturate for a few cycles once the led channels are re- enabled. table 5. operation current consumption modes mode en pin sck/sda pins i 2 c bit command current consumption mode comments manual low low n/a shutdown high low n/a operational sm bus low low (> 27 ms) en bit = x shutdown low active en bit = 0 sleep low active en bit = 1 operational i 2 c low x seti2c bit = 1 i 2 c low power (shutdown) part doesn?t wake-up clri2c bit = 0 en bit = x high x seti2c bit = 1 sleep clri2c bit = 0 en bit = 0 high x seti2c bit = 1 operational clri2c bit = 0 en bit = 1 v out method 1 method 2 a0/sen a0/sen ovp = v zener2 + 6.5 v ovp = 6.5 v [(r upper / r lower ) + 1] + (100e-6 x r upper ) r upper r lower v zener2
analog integrated circuit device data freescale semiconductor 18 34844 functional description functional internal block description mc34844 also the device has a precha rge voltage that add 0.5 volts to the boost, cycle by cycle of t he pwm. it help s the boost to respond faster every time the load turns back on again. current mirror the programmable current mirr or matches the current in 10 led strings to within 2%. the maximum current is set using a resistor to gnd from t he iset pin. this can be scaled down using the i 2 c interface to 255 levels. zero current is achieved by turning off the led driver by i 2 c (registers chenx = 0 h) for a duty cycle from 0% to 99% or by pulling pwm pin low regardless of the duty cycle. i 2 c capability allows the channels to be controlled individually or in parallel. current on led channel (pin and nin mode disabled) eqn. 1 in the off state, the leds current is set to 0 and the boost converter stops switching. this feature allows to drive more than 50 ma of current by connecting the led string to 2 or more led channels in parallel. for example; if the application requires to drive 5 channels at 100 ma, then the bottom of each led string should be connected to two channels in order to duplicate the current capability (example: ch0+ch1 = 100 ma). pwm generator the pwm generator can operate in either master or slave modes, as set by the m/~s pin. in master mode, the internal pwm generator frequency is programmed through the i 2 c interface (registers fpwm). the default programmed value set the number of 25 khz clocks (40 s) in one pwm cycle. the 18-bit resolution allows minimum pwm frequencies of 100 hz to be programmed. the resulting frequency is output on the ck pin. pwm frequency eqn. 2 in slave mode, the ck pin acts as an input. the internal digital pll uses this frequency as the pwm frequency. by setting one device as master , and connecting the ck output to the input on a number of slave configured devices, all pwm frequencies are synchronized together. the duty cycle of the pwm wave form in both master and slave modes is set using a second register on the i 2 c interface (register dpwm), and can be controlled from 100% duty cycle to 1/256 t pwm = 0.39%. zero percent of duty cycle is achieved by turning led drivers off (register chenx = 0h) or pulling pwm pin low. an external pwm can also be used. the pwm input is 'and'ed with the internal signal. by setting the serial interface to 100% duty cycle (default), the external pin has full control of the pwm duty cycle. this pin can also be used to modulate the led at a lower frequency than the pwm dimming frequency (minimum pulse width = 150 ns). a pulsed mode can also be programmed using the i 2 c interface (strobe bit = 1). in this mode, each rising edge of the pwm signal turns on the next channel, while turning off all other channels. the duration that the channel is illuminated is set by the duty cycl e of the pwm in put pin. this can be used to scan the output channels. disabling led channels the 34844 allows the user to enable and disable each of the 10 channels separately by writing the corresponding chenx bit on registers 08 and 09 thru i 2 c. when a channel is disabled thru the i 2 c prior the device starts to operate, the correspon ding led driver is disabled but the feedback circuit is stil l connected. this may interfere with the operation of the dynam ic headroom control (dhc) which can lead to erratic output voltage regulation. for this condition, the output voltage ma y ramp up to the ovp level if the voltage on the led driver is not substantially above the dhc regulation voltage (0.75 v typ). because of this operation under i 2 c/smbus mode, we recommend to connect the unused channels to vdc2 thru a100 kohm resistor and also follow the below powering up sequence: 1. pwm pin = low. 2. power up the part. 3. program the i 2 c commands and disable the unused channels. 4. enable the boost and current drivers by taking pwm pin to high. this previous device's operation does not happen when all channels are being used because the voltage across the led drivers is always equal or higher than the dhc regulation voltage (0.75 v typ). for this condition, the user can disable/ enable any of the channels thru i 2 c without causing any erratic behavior but the fail pin cannot be cleared. if fail pin is to be cleared thru i 2 c, it will be necessary to use the suggested configuration show n at the fail pin session. fail pin if a led fails open in any of the led strings, the voltage in that particular led channel will be close to ground and the led open failure is detected. w hen this happens, a failure is registered, the fail pin is set to its high-impedance stage, and the channel is turned off. the fail pin cannot be cleared for manual mode unless a complete power on reset is applied. however for i 2 c/smbus mode, the fail pin is cleared by disabling the malfunction channels (chenx = 0) and clearing the failure bit (clrfail bit = 1). if the application only requires clearing the failure for the floating or unused channels, then the unused channels must be connected to vdc2 thru a 100 kohm resistor to avoid reach instability problems. this will allow detecting another failure from the connected channels. (see figure 6 ) current a [] ich registervalue [] rset ohms [] ----------------------------------------------------------- = pwmfrequency hz [] 19.2mhz fpwm registervalue [] ------------------------------------------------------------------- - =
analog integrated circuit device data 19 freescale semiconductor 34844 functional description functional internal block description mc34844 figure 6. single channel disconnect circuit. for applications where multiple failure detection is required, then one 100 kohm resistor must be placed from each channel to a diode (d2) connected to vdc2. the resistor will provide a pull up voltage to the disconnected channels so that they do not interfere with the dhc circuit. the diode (d2) ensures that when the connected channels are in pwm off state the led strings do no conduct current to vdc2. (see figure 7 ) figure 7. resistor/diode placement for multiple open circuit detection if the fail pin cannot be cleared by software then it indicates that the failure is because of t an over-current in the boost. since this is a critical failure the only way to clear it is by releasing the part from the ov er-current condition and then shutdown the part (refer to table 5 ) if i 2 c communication is not presen t, fail condition should be reset by removing the failure and re-enabling the device thru the en pin. optical and temperature control loop the 34844 supports both optic al and temperature loop control. for temperature loop control, the led brightness can be adjusted depending on the tem perature of the leds. for optical loop control, the 34844 supports both optical closed loop backlight control, where the brightness of the backlight is maintained at a required level by adjusting the light output, until the desir ed level is achieved, or with ambient light control, wher e the backlight brightness increases as ambient light increases. both temperature and optical loops are supported through the pin and nin pins. each pin supports a 0-2.048 v input range which affects the current through the leds. the pin pin increases current as the voltage rises from 0-2.048 v. the nin pin reduces current as the voltage rises from 0- 2.048 v. a 10.2 k resistor or higher value must be used at the iset pin if the part is configured to use pin+nin control loop functionality, the 50 ma maximum current is achieved at the higher allowed level of pin/nin pins, ensuring the maximum current of the led dr ivers are not exceeded. the optical and temperature co ntrol loop can be disabled by i 2 c setting bits (pinen & nine n), or by tying pin and nin pins high (>2.2 v) it is called v set mode, and the led driver maximum current is set to 50 ma by using a 5.1 k resistor at the iset pin. current on led channel (pin mode) eqn. 3 current on led channel (nin mode) eqn. 4 current on led channel (pin+nin mode) eqn. 5 led failure protection open led protection if led fails open in any of the led strings, the voltage in that channel will be pulled close to zero, which will cause the channel to be disabled. as a result, the boost output voltage will go to the ovp level and then come down to the regulation level to continue powering t he rest of the led strings. short led protection if an led shorted in any of the led strings, the device will continue to operate without in terruption. however, if the current a [] vpin ich registervalue [] () rset ohms [] 2 --------------------------------------------------------------------------------------- - = current a [] 2.048 vnin ? () ich registervalue [] rset ohms [] 2 ------------------------------------------------------------------------------------------------------------- = current a [] 2.048 vnin ? vpin + () ich registervalue [] rset ohms [] 2 ------------------------------------------------------------------------------------------------------------------------------- --- - =
analog integrated circuit device data freescale semiconductor 20 34844 functional description functional internal block description mc34844 shorted led happens to be in the led string with the highest forward voltage, the dhc circuit will automatically regulate the output voltage with respect to the new highest led voltage. if more leds are short ed in the same led string, it may cause excessive power dissipation in the channel which may cause the ott circuit to trip which will completely shutdown the device. over-temperature protection the 34844 has an on-chip te mperature sensor that measures die temperature. if the ic temperature exceeds the ott threshold, the ic will turn off all power sources inside the ic (led drivers, boost and internal regulators) until the temperature falls below the fa lling ott threshold. once it comes back on, it will operate with the default configuration (refer to table 7 ). serial interface control the 34844 uses an i 2 c interface capable of operating in standard (100 khz) or fast (400 khz) modes. the a0/sen pin can be used an address select pin to allow more than 2 devices in the system. the a0/sen pin should be held low on all chips expect the one to be addressed, where it is taken high.
analog integrated circuit device data 21 freescale semiconductor 34844 functional device operation operational modes mc34844 functional device operation operational modes normal mode in normal operation the 34844 is programed via i 2 c to drive up to 50 ma of current through each one of the led channels. the 34844 can be configured in master or slave mode as set by the m/~s pin. in master mode , the internal pwm generator frequency is programmed through the i 2 c interface. the programmed value sets the number of 25 khz clocks (40 s) in one pwm cycle. the 18-bit resolution allows minimum pwm frequencies of 100 hz to be programmed. the resulting frequency is output on the ck pin. in slave mode, the ck pin acts as an input. the internal digital pll uses this frequency as the pwm frequency. by setting one device as a master, and connecting the ck output to the input on a number of slave configured devices, all pwm frequencies are synchronized together. for this application a0/sen pin indicates which device is enable for i 2 c control. in slave mode , an internal phase lock loop will lock the internal pwm generator period to the period of the signal present at the ck pin. the pll can lock to any frequency from 100 hz to 25 khz provided the jitter is below 1000 ppm. at frequencies above 1.0 khz, the pll will maintain lock regardless of the transient power conditions imposed by the user (i.e. going from 0% duty cycle to 100% at 20w led display power). below 1.0 khz, thermal time constants on the die are such that the pll may momentarily lose lock if the die temperature changes substantially during a large load power step. as explained below, this anomaly can be avoided by controlling the rate of change in pwm duty cycle. to better understand this issue, consider that the on chip pll uses a vco that is subject to thermal drift on the order of 1000 ppm/c. further consider that the thermal time constant of the chip is on the order of single digit milliseconds. therefore, if a lar ge power load step is imposed by the user (i.e. going from 0% duty cycle to 100% duty cycle with a load power of 20 w), the die will experience a large temperature wave gradient that will propagate across the chip surface and thereby affect the instantaneous frequency of the vco. as long as such changes are within the bandwidth of the pll, the pll will be able to track and maintain lock. exceeding this rate of change may cause the pll to lose lock and the backlight will momentarily be blanked until lock is reacquired. at 100 hz lock, the pll has a b andwidth of approximately 10 hz. this means that temperat ure changes on the order of 100 ms are tolerable without losing lock. but full load power changes on the order of 10 ms (i.e. 100 hz pwm) are not tracked out and the pll can momentarily lose lock. if this happens, as stated above, the led drivers are momentarily disabled until lock is reacquired. this will be manifested as a perceivable short flash on the backlight immediately after the load change. to avoid this problem, one can simply limit large instantaneous changes in die temperature by invoking only small power steps when raising or lowering the display power at low pwm frequencies. for exam ple, to maintain lock while transitioning from 0% to 100% duty cycle at 20 w load power and a pwm frequency of 100 hz would entail stepping the power at a rate not to exceed 1% per 10 ms. if a load of less than 20 w is used, then the rate of rise can be increased. as the locked pwm frequency increases (i.e. use 600 hz instead of 100 hz), the step rate can be further increased to approximately 4% per 2.0 ms. the exact step rate to avoid loss of pll lock is a function of essentially three things: (a) the composite thermal resistance of the user's pcb assembly, (b) the load power, and (c) the pwm frequency. for all cases below 1.0 khz, simply using a rate of 1% duty cycle change per pwm period will be adequate. if this is too slow, the value can be optimized experimentally once the hardware design is complete. at pwm rates above 1.0 khz, it is not necessary to control the rate of change in pwm duty cycle. it is important to point out that when operating in the master mode, one does not need to concern themselves with loss of lock since the reference clock and the vco clock are collocated on the die, and th erefore experience the same thermal shift. hence in master mode, once lock is initially acquired, it is not lost and no blanking of the display occurs. the duty cycle of the pwm in both master and slave mode is set using a second register on the i 2 c interface. an external pwm signal can also be applied in the pwm pin. this pin is and?ed with the internal signal, giving the ability to contro l the duty cycle either via i 2 c or externally by setting any of the 2 signals to 100% duty cycle. strobe mode a strobe mode can be programmed via i 2 c. in this mode, each rising edge of the pwm signal turns on the next channel, while turning off all other channels. the duration that the channel is illumi nated is set by the duty cycle of the pwm input pin. this mode can be also programmed by controlling the on and off state of each led channel via i 2 c. manual mode the 34844 can also be used in manual mode without using the i 2 c interface. by setting the pin m/~s high, the led dimming will be controlled by the external pwm signal. the over-voltage protection limit can be settled by a resistor divider on a0/sen pin.
analog integrated circuit device data freescale semiconductor 22 34844 functional device operation i2c bus specification mc34844 during manual mode, all internal registers are in default configuration, refer table 7 , under this configuration the pin and nin pins are enabled to scale the current capability per string and may be disable by setting 2.2 v in the corresponding pin. also in this mode, the device can be enabled as follows: + en pin + pwm signal (two signals): in this configuration, the pwm signal applied to pwm pin will be in charge of controlling the led dimming and a second signal will enable or disable the chip through the en pin. figure 21 + pwm signal tied to sda pin (just one signal): in this configuration the pwm pin should be tied to sda pin. the pwm signal applied to pwm pin will be in charge of controlling led dimming and enable the device every time the pwm is active. for this configuration en pin should be low. power down mode if the input voltage falls below the uvlo threshold, the device enters automatically into power down mode. when in power down, the supply current is reduced below 2.0 a when there is no i 2 c activity, and it rises up when i 2 c interface is enabled. i 2 c bus specification the 34844 is a unidirectional device that can only be written by an external control unit. since the device is a 7 bit address device (1110110), the control unit needs to follow a sp ecific data transfer format which is shown in figure 8 . figure 8. a complete data transfer for a complete data transfer, please use this format in the following order: 1. start condition 2. the 34844 device address and write instruction (r/w = 0) 3. first data pack, it corresponds to the 34844 register that needs to be written. (refer to table ) 4. second data pack, it corresponds to the value that should be written to that register. (refer to table ) 5. stop condition i 2 c variables description: ? start: this condition occurs when sda changes from high to low while sck is high. ? acknowledge: the acknowledge clock pulse is generated by the master (control unit). ? the transmitter releases the sda line (high) during the acknowledge clock pulse. the receiver (34844) must pull down the sda line during this acknowledge pulse to indicate that the data was correctly written. ? bits in the first byte: the firs t seven bits of the first bite make up the slave address. the eighth bit is the lsb (least significant bit), which dete rmines the direction of the message (write = 0) for the 34844 device, when an address is sent, each of the devices in a system compares t he first seven bits after the start condition with its addr ess. if they match, the device considers itself addre ssed by the control unit as a slave-receiver. ? stop: this condition occurs when sda changes from low to high while sck is high for more inform ation about ?i 2 c bus specification? please refer to the following link: http://www.nxp.com/acrob at_download/literature/ 9398/39340011.pdf
analog integrated circuit device data 23 freescale semiconductor 34844 functional device operation logic commands and registers mc34844 logic commands and registers table 6. write registers reg / db d7 d6 d5 d4 d3 d2 d1 d0 00 ovp3 ovp2 ovp1 ovp0 ninen pinen en 01 clri2c seti2c 04 fpwm5 fpwm4 fpwm3 fpwm2 fpwm1 fpwm0 05 fpwm11 fpwm10 fpwm9 fpwm8 fpwm7 fpwm6 06 fpwm17 fpwm16 fpwm15 fpwm14 fpwm13 fpwm12 07 dpwm7 dpwm6 dpwm5 dpwm4 dpwm3 dpwm2 dpwm1 dpwm0 08 chen4 chen3 chen2 chen1 chen0 09 strb clrfail all_off chen9 chen8 chen7 chen6 chen5 14 bst1 bst0 f0 ich0_7 ich0_6 ich0_5 ich0_4 ich0_3 ich0_2 ich0_1 ich0_0 f1 ich1_7 ich1_6 ich1_5 ich1_4 ich1_3 ich1_2 ich1_1 ich1_0 f2 ich2_7 ich2_6 ich2_5 ich2_4 ich2_3 ich2_2 ich2_1 ich2_0 f3 ich3_7 ich3_6 ich3_5 ich3_4 ichg_3 ich3_2 ich3_1 ich3_0 f4 ich4_7 ich4_6 ich4_5 ich4_4 ich4_3 ich4_2 ich4_1 ich4_0 f5 ich5_7 ich5_6 ich5_5 ich5_4 ich5_3 ich5_2 ich5_1 ich5_0 f6 ich6_7 ich6_6 ich6_5 ich6_4 ich6_3 ich6_2 ich6_1 ich6_0 f7 ich7_7 ich7_6 ich7_5 ich7_4 ich7_3 ich7_2 ich7_1 ich7_0 f8 ich8_7 ich8_6 ich8_5 ich8_4 ich8_3 ich8_2 ich8_1 ich8_0 f9 ich9_7 ich9_6 ich9_5 ich9_4 ich9_3 ich9_2 ich9_1 ich9_0 fa ichg_7 ichg_6 ichg_5 ichg_4 ichg_3 ichg_2 ichg_1 ichg_0 table 7. register description register name default value (hex) description en 1 chip enable by software. this signal is ?or?ed with external en (0=off, 1 =on) pinen 1 pin pin enable (0=off, 1 =on) ninen 1 nin pin enable (0=off, 1 =on) ovp[3:0] f ovp voltage seti2c 0 set i 2 c communication (disable sm bus mode) clri2c 0 clear set i 2 c fpwm[17:0] 300 pwm frequency dpwm[7:0] ff pwm duty cycle (ffh =100%) chen[9:0] 3ff channel enable (0=off, 1=on) all_off 0 all 10 channels off at the same. in order to reactivate channels this bit should be clear. clrfail 0 clear fail if channels are re-enable. strb 0 strobe mode (0=parallel, 1=strobe)
analog integrated circuit device data freescale semiconductor 24 34844 functional device operation logic commands and registers mc34844 bst[1:0] 2 boost frequency (150,300,600,1200 khz) [0h=150 hz] ich#[7:0] ff channel current program (ffh = maximum current) ichg[7:0] ff global current program table 8. over-voltage protection register (hex) ovp value (volts) 2 11 3 15 4 19 5 23 6 27 7 31 8 35 9 39 a 43 b 47 c 51 d 55 e 59 f 62 table 7. register description register name default value (hex) description
analog integrated circuit device data 25 freescale semiconductor 34844 functional device operation typical performance curves (ta=25c) mc34844 typical performance curves (t a =25c) figure 9. boost efficiency vs input voltage figure 10. line regulation, v in changing 85% 86% 87% 88% 89% 90% 91% 92% 93% 94% 95% 10 12 14 16 18 20 22 24 26 28 30 vin, volts efficiency (%) fs = 600khz l=22uh, dcr=52mo schottky v12p10-e3/86a c out = 2x4.7f, 2x2.2f/100v fpwm=600hz, 100% duty load = 16 leds, 50ma/channel v led = 48v, 1v /channel 50.00 50.05 50.10 50.15 50.20 50.25 50.30 50.35 50.40 50.45 50.50 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 vin, volts iled (highest v led channel), ma fs = 600khz l=22uh, dcr=52mo schottky v12p10-e3/86a c out = 2x4.7f, 2x2.2f/100v fpwm=600hz, 100% duty load = 16 leds, 50ma/channel v led = 48v, 1v /channel
analog integrated circuit device data freescale semiconductor 26 34844 functional device operation typical performance curves (ta=25c) mc34844 figure 11. pwm dimming linearity figure 12. bias current vs input voltage (operational mode) 12.46 ma 0.14 ma 50.01 m a 37.59 ma 25.03 m a 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 50.0 0.4% 25.0% 50.0% 75.0% 99.6% pwm duty cycle (%) led current, ma fpwm=25khz 9.90 9.92 9.94 9.96 9.98 10.00 10.02 10.04 10.06 10.08 10.10 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 vin, volts bias current, ma i2 c mo de sm_bus mode manual mode
analog integrated circuit device data 27 freescale semiconductor 34844 functional device operation typical performance curves (ta=25c) mc34844 figure 13. bias current vs input voltage (sleep mode) figure 14. boost soft start 2.98 3.00 3.02 3.04 3.06 3.08 3.10 3.12 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 vin, volts bias current, ma i2c mode sm_bus mode vout comp induc tor current vin=24 v l oad =16 l ed s, 5 0ma/cha nne l vled = 47v, 1v vout comp induc tor current vin=24 v l oad =16 l ed s, 5 0ma/cha nne l vled = 47v, 1v
analog integrated circuit device data freescale semiconductor 28 34844 functional device operation typical performance curves (ta=25c) mc34844 figure 15. typical operation waveforms for fpwm=600 hz, 40% duty figure 16. typical operation waveforms for fpwm=600 hz, 100% duty iled, ch1 inductor current vch1 vout (ac coupled) iset=40ma (all channels) fpwm=600hz, 40% duty precharge iled, ch1 inductor current swa swb iset=50ma (all channels) fpwm=600hz, 100% duty (ac coupled) vout iled, ch1 inductor current swa swb iset=50ma (all channels) fpwm=600hz, 100% duty (ac coupled) vout
analog integrated circuit device data 29 freescale semiconductor 34844 functional device operation typical performance curves (ta=25c) mc34844 figure 17. low duty dimming operation waveforms (fpwm=20 khz, 2lsb) figure 18. low duty dimming operation waveforms (fpwm=20 khz, 1lsb) iset = 20ma, fpwm=20khz, duty=0.78% (2lsb) vch1 iled1 iset = 20ma, fpwm=20khz, duty=0.78% (2lsb) vch1 iled1 iset = 20ma, fpwm=20khz, duty=0.78% (2lsb) vch1 iled1 iset = 20ma, fpwm=20khz, duty=0.39% (1lsb) vch1 iled1 iset = 20ma, fpwm=20khz, duty=0.39% (1lsb) vch1 iled1 iset = 20ma, fpwm=20khz, duty=0.39% (1lsb) vch1 iled1
analog integrated circuit device data freescale semiconductor 30 34844 typical applications mc34844 typical applications figure 19. manual mode (single wire control) figure 20. manual mode (two wire control) vin = 24v 0 0 0 vout 0 0 0 0 vdc1 vdc1 vcc 0 vout master ck led matrix (16s10p) manual mode (single wire control) output ovp = 55v 5.6k 5.6k + 47uf + 47uf 2.2uf 2.2uf 3.3k 3.3k 20k 20k 309k 309k 5.1k 5.1k + 13.8uf + 13.8uf 150k 150k 1.8nf 1.8nf u1 34844 u1 34844 vin 1 vdc1 28 comp 29 en 7 ck 24 m/~s 30 pwm 25 sck 27 sda 26 a0/sen 6 iset 19 pin 20 nin 21 swa 4 swb 3 vout 32 pgnda 5 pgndb 2 vdc2 31 fail 18 i0 8 i1 9 i2 10 i3 11 i4 12 i5 13 i6 14 i7 15 i8 16 i9 17 vdc3 23 slope 22 gnd 33 56pf 56pf clk clk d1 d1 2 1 2.2uf 2.2uf 22uh 22uh 1 2 2.2uf 2.2uf 1.0k vin = 24v 0 0 0 0 vcc vout vout 0 vdc1 vdc1 0 0 0 master ck output led matrix (16s10p) ovp = 55v manual mode (two wire control) unit control en pwm 2.2uf 2.2uf d5 d5 2 1 22uh 22uh 1 2 1.8nf 1.8nf 2.2uf 2.2uf 3.3k 3.3k 150k 150k + 13.8uf + 13.8uf u2 34844 u2 34844 vin 1 vdc1 28 comp 29 en 7 ck 24 m/~s 30 pwm 25 sck 27 sda 26 a0/sen 6 iset 19 pin 20 nin 21 swa 4 swb 3 vout 32 pgnda 5 pgndb 2 vdc2 31 fail 18 i0 8 i1 9 i2 10 i3 11 i4 12 i5 13 i6 14 i7 15 i8 16 i9 17 vdc3 23 slope 22 gnd 33 2.2uf 2.2uf 20k 20k 5.1k 5.1k 5.6k 5.6k 56pf 56pf + 47uf + 47uf 309k 309k 1.0k
analog integrated circuit device data 31 freescale semiconductor 34844 typical applications mc34844 figure 21. sm bus mode figure 22. master - slave connection vin = 24v 0 0 0 0 vcc vout 0 vdc1 vdc1 0 0 vdc1 0 master ck led matrix (16s10p) unit control sck sda + 47uf + 47uf 309k 309k 2.2uf 2.2uf d8 d8 2 1 22uh 22uh 1 2 1.8nf 1.8nf 2.2uf 2.2uf 3.3k 3.3k + 13.8uf + 13.8uf u3 34844 u3 34844 vin 1 vdc1 28 comp 29 en 7 ck 24 m/~s 30 pwm 25 sck 27 sda 26 a0/sen 6 iset 19 pin 20 nin 21 swa 4 swb 3 vout 32 pgnda 5 pgndb 2 vdc2 31 fail 18 i0 8 i1 9 i2 10 i3 11 i4 12 i5 13 i6 14 i7 15 i8 16 i9 17 vdc3 23 slope 22 gnd 33 2.2uf 2.2uf 5.1k 5.1k 5.6k 5.6k 56pf 56pf 1.0k vin = 24v 0 0 0 0 vcc vout 0 vdc1 vdc1 0 0 vdc1 vin = 24v 0 0 0 0 vcc vout 0 vdc1 0 0 vdc1 master ck master ck led matrix (16s10p) unit control sck sda a0/sen (master) master - slave connection master device slave device input led matrix (16s10p) a0/sen (slave) 56pf 56pf 2.2uf 2.2uf u5 34844 u5 34844 vin 1 vdc1 28 comp 29 en 7 ck 24 m/~s 30 pwm 25 sck 27 sda 26 a0/sen 6 iset 19 pin 20 nin 21 swa 4 swb 3 vout 32 pgnda 5 pgndb 2 vdc2 31 fail 18 i0 8 i1 9 i2 10 i3 11 i4 12 i5 13 i6 14 i7 15 i8 16 i9 17 vdc3 23 slope 22 gnd 33 3.3k 3.3k 5.1k 5.1k 309k 309k u4 34844 u4 34844 vin 1 vdc1 28 comp 29 en 7 ck 24 m/~s 30 pwm 25 sck 27 sda 26 a0/sen 6 iset 19 pin 20 nin 21 swa 4 swb 3 vout 32 pgnda 5 pgndb 2 vdc2 31 fail 18 i0 8 i1 9 i2 10 i3 11 i4 12 i5 13 i6 14 i7 15 i8 16 i9 17 vdc3 23 slope 22 gnd 33 2.2uf 2.2uf + 47uf + 47uf 22uh 22uh 1 2 5.6k 5.6k 22uh 22uh 1 2 2.2uf 2.2uf d1 d1 2 1 56pf 56pf + 13.8uf + 13.8uf 3.3k 3.3k 309k 309k 5.1k 5.1k + 47uf + 47uf 2.2uf 2.2uf 1.8nf 1.8nf 2.2uf 2.2uf d2 d2 2 1 + 13.8uf + 13.8uf 1.8nf 1.8nf 2.2uf 2.2uf 5.6k 5.6k 1.0k 1.0k
analog integrated circuit device data freescale semiconductor 32 34844a mc34844a specifications pages 32 to 54 mc34844a mc34844a specifications pages 32 to 54
analog integrated circuit device data freescale semiconductor 33 34844a internal block diagram mc34844a internal block diagram figure 23. 34844a simplified internal block diagram vin vdc1 comp en ck pwm sck sda iset pin nin swa swb pgnda fail i0 i1 i2 i3 i4 i5 i6 i7 i8 i9 temp/opto loop control current dac ocp/otp/uvlo pwm generator 10 channel ovp boost clock/pll controller 80 ma current mirror v sense gnd a0/sen pgndb ldo vdc3 vdc2 slope i 2 c interface vout m/~s
analog integrated circuit device data 34 freescale semiconductor 34844a pin connections mc34844a pin connections figure 24. 34844a pin connections table 9. 34844a pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 42 . pin number pin name pin function formal name definition 1 vin power input voltage input supply 2 pgndb power power ground power ground 3 swb input switch node b boost switch connection b 4 swa input switch node a boost switch connection a 5 pgnda power power ground power ground 6 a0/sen input device select address select, device select pin or ovp hw control 7 en input enable enable pin (active high, internal pull-up) 8 - 17 i0-i9 input led channel led string connections 18 fail open drain fault detection fault detected pin (open drain): no failure = low-impedance failure = high-impedance 19 iset passive current set led current setting resistor 20 pin input positive current scale positive input analog current control 21 nin input negative current scale negative input analog current control 22 slope passive boost slope boost slope compensation setting resistor 23 vdc3 output internal regulator 3 decoupling capacitor for internal phase locked loop power 24 ck input/output clock signal clock synchronization pin (input for m/~s = low - internal pull-up, output for m/~s = high) 25 pwm input external pwm external pwm input (internal pull-down) vin pgndb swb swa pgnda a0/sen en io ck vdc3 slope nin pin iset fail i9 vout vdc2 m/~s comp vdc1 sck sda pwm i1 i2 i3 i4 i5 i6 i7 i8 25 32 31 30 29 28 27 26 24 17 18 19 20 21 22 23 1 8 7 6 5 4 3 2 16 9 101112131415 qfn - ep 5mm x 5mm 32 lead ep gnd ep = exposed pad transparent top view
analog integrated circuit device data freescale semiconductor 35 34844a pin connections mc34844a 26 sda bidirectional i 2 c data i 2 c data line 27 sck bidirectional i 2 c clock i 2 c clock line 28 vdc1 output internal regulator 1 decoupling capacitor fo r internal logic rail 29 comp passive compensation pin boost converter type compensation pin 30 m/~s input master/slave selector selects master mode (1) or slave mode (0) 31 vdc2 output internal regulator 2 decoupling capacitor for internal regulator 32 vout input voltage output boost output voltage sense pin ep gnd - ground ground reference for all internal circuits other than boost fet table 9. 34844a pin de finitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 42 . pin number pin name pin function formal name definition
analog integrated circuit device data 36 freescale semiconductor 34844a electrical characteristics maximum ratings mc34844a electrical characteristics maximum ratings table 10. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings maximum pin voltages a0/sen i0, i1, i2, i3, i4, i5, i6, i7, i8, i9 (17) en, vin swa, swb, vout fail, pin, nin, iset, m/~s, ck, pwm v max 7.0 45 30 65 6.0 v maximum led current i max 85 ma esd voltage (14) human body model (hbm) machine model (mm) v esd + 2000 + 200 v thermal ratings ambient temperature range t a -40 to 105 c junction to ambient temperature (15) t ja 32 c/w junction to case temperature (15) t jc 3.5 c/w maximum junction temperature t j 150 c storage temperature range t sto -40 to 150 c peak package reflow temperature during reflow (16) t pprt 260 c power dissipation ta = 25c ta = 70c ta = 85c ta = 105c 3.9 2.5 2.0 1.4 w notes 14. esd testing is performed in accordance with the human body model (hbm) (aec-q100-2), and the machine model (mm) (aec-q100- 003), r zap = 0 15. per jedec51 standard for multilayer pcb 16. pin soldering temperature limit is for 10 seconds maximum dur ation. not designed for immersion soldering. exceeding these li mits may cause malfunction or permanent damage to the device. 17. 45 v is the maximum allowable voltage on all led channels in off-state.
analog integrated circuit device data freescale semiconductor 37 34844a electrical ch aracteristics static and dynamic elec trical characteristics mc34844a static and dynamic electrical characteristics table 11. static and dynamic el ectrical characteristics characteristics noted under conditions v in = 12 v, v out = 42 v, pwm = vdc1, m/~s = vdc1, pin & nin = vdc1, -40 c t a 105 c, pgnd = 0 v, unless otherwise noted. characteristic symbol min typ max unit supply supply voltage (20) v in 7.0 12 28 v supply current when shutdown mode manual: pwm = low, en = low, sck & sda=low sm bus: en bit = 0, sck & sda=low, en pin= low i 2 c: seti2cbit=1, clri2c=0, en bit= 0, en pin = low i shutdown - - 2.0 17 - - a supply current when sleep mode sm-bus: en = low, sck & sda= active, seti2c bit = 0, en bit = 0 i 2 c: en = high, seti 2 c bit = 1, clri 2 c bit = 0, en bit = 0 i sleep - 4.0 - ma supply current when operational mode manual: en= high, sck & sda=low, pwm=low sm-bus: en= low, sck & sda=active, en bit= 1, pwm=low i 2 c: en = high, seti 2 c bit = 1, clri 2 c bit = 0, en bit = 1, pwm=low i operational - 13.0 - ma under-voltage lockout (v in rising) uvlo 5.4 6.0 6.4 v under-voltage hysteresis (v in falling) uvlo hyst - 300 - mv vdc1 voltage (18) c vdc1 = 2.2 f v dc1 2.3 2.5 2.75 v vdc2 voltage (18) c vdc2 = 2.2 f v dc2 5.5 6.0 6.5 v vdc3 voltage (18) c vdc3 = 2.2 f v dc3 2.3 2.5 2.75 v boost output voltage range (19) (20) vin = 7.0 v vin = 28 v v out1 v out2 8.0 32 - - 28 60 v boost switch current limit i fet 2.3 2.5 2.7 a boost switch current limit timeout t boost_time - 10 - ms rdson of internal fet (i drain = 1.0 a) r dson - 250 500 m boost switch off-state leakage current v swa,swb = 65 v i boost_leak - - 10 a feedback pin off-state leakage current (v out = 65 v ) vout leak - 500 700 a peak boost efficiency (20) eff boost - 90 - % notes 18. this output is for internal use only and not to be used for other purposes. a 1.0 k resistor between the vdc3 and vdc1 pin is recommended for <-20 c operation. 19. minimum and maximum output voltages are dependent on min/max duty cycle and current limit condition. 20. guaranteed by design
analog integrated circuit device data 38 freescale semiconductor 34844a electrical characteristics static and dynamic electrical characteristics mc34844a line regulation (21) - vin=7.0 to 28 v i out /v in -0.2 - 0.2 %/v load regulation (21) - vled = 8.0 to 65 v (all channels) i out /v led -0.2 - 0.2 %/v slope compensation voltage ramp - r slope = 68 k v slope - 0.49 - v/ s current sense amplifier gain a csa - 9.0 - current sense resistor r sense - 22 - m ota transconductance g m - 200 - s transconductance sink and source current capability i ss - 100 - a fail pin off-state leakage current - v fail = 5.5 v i fail_leak - - 50 a on-state voltage drop - i sink = 4.0 ma v ol - - 0.4 v led channels sink current ichx register = 255, pin&nin = disabled, t a =25 c riset=3.48 k , 0.1% i sink 78.4 80 81.6 ma regulated minimum voltage across drivers pulse width > 400 ns v min 625 700 775 mv current matching accuracy i match -2.0 - 2.0 % i set pin voltage riset=3.48 k , 0.1% v set 2.007 2.048 2.069 v led current amplitude resolution 1.0 ma < i led < 80 ma iled res - 1.5 - % off-state leakage current, all channels - (v ch = 45 v) i ch_leak - - 10 a pin input voltage to disable pin mode v pin_dis 2.2 - - v pin bias current pin = v set i pin -2.0 - 2.0 a analog dimming current ichx register = 255, riset=3.48 k 0.1% pin = v set /2 pin = v set i dim_pin 36 76 40 80 44 84 ma notes 21. guaranteed by design table 11. static and dynamic elec trical characteristics (continued) characteristics noted under conditions v in = 12 v, v out = 42 v, pwm = vdc1, m/~s = vdc1, pin & nin = vdc1, -40 c t a 105 c, pgnd = 0 v, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 39 34844a electrical ch aracteristics static and dynamic elec trical characteristics mc34844a nin input voltage to disable nin mode v nin_dis 2.2 - - v nin bias current nin = v set i nin -2.0 - 2.0 a analog dimming current ichx register = 255, riset=3.48 k 0.1% nin = v set /2 nin = 0 v i dim_nin 36 76 40 80 44 84 ma over-temperature protection over-temperature threshold (22) rising hysteresis o tt 150 - 165 25 175 - c i 2 c/sm bus physical layer [sck, sda] i 2 c address adr i2c - 1110110 - binary sm-bus address adr smb - 1110110 - binary input low voltage v ili -0.3 - 0.8 v input high voltage v ihi 2.1 - 5.5 v input hysteresis v hysi - 0.3 - v output low voltage sink current < 4.0 ma v oli - - 0.4 v input current i ini -5.0 - 5.0 a input capacitance (22) c ini - - 10 f logic inputs / outputs (ck, m/~s, pwm, a0/sen, en) input low voltage v ill -0.3 - 0.5 v input high voltage v ihl 1.5 - 5.5 v input hysteresis v hysl - 0.1 - v input low voltage (en) v ill -0.3 - 0.5 v input high voltage (en) v ihl 2.1 - 28 v output low voltage (ck) i sink < 2.0 ma v oll - - 0.45 v output high voltage (ck) i source < 2.0 ma v ohl 2.2 - 5.5 v input current i iil -5.0 - 5.0 a input capacitance (22) c ini - - 5.0 f notes 22. guaranteed by design table 11. static and dynamic elec trical characteristics (continued) characteristics noted under conditions v in = 12 v, v out = 42 v, pwm = vdc1, m/~s = vdc1, pin & nin = vdc1, -40 c t a 105 c, pgnd = 0 v, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 40 freescale semiconductor 34844a electrical characteristics static and dynamic electrical characteristics mc34844a over-voltage protection over-voltage clamp - ovp register table: ovp = fh (default) ovp fh 60.5 62.5 64.5 v ovp = eh ovp eh 56.5 58 60 v ovp = dh ovp dh 53 54 56 v ovp = ch ovp ch 49 51 52.5 v ovp = bh ovp bh 45 47 48.5 v ovp = ah ovp ah 41 43 44.5 v ovp = 9h ovp 9h 38 39 40.5 v ovp = 8h ovp 8h 34 36 37.5 v ovp = 7h ovp 7h 30.5 32 33.5 v ovp = 6h ovp 6h 26 28 30 v ovp = 5h ovp 5h 23 24 25 v over-voltage threshold, set by hardware, voltage at a0/sen ovp hw 6.15 6.5 6.85 v a0/sen sink current, t a =25c i sink_ovp 70 100 130 a boost switching frequency (bst [1:0]=0) f sw0 0.14 0.16 0.18 mhz switching frequency (bst [1:0]=1) (default) f sw1 0.29 0.32 0.35 mhz switching frequency (bst [1:0]=2) f sw2 0.59 0.65 0.72 mhz switching frequency (bst [1:0]=3) f sw3 1.17 1.30 1.42 mhz boost switching frequency f sw 0.29 0.32 0.35 mhz minimum duty cycle d min - 10 15 % maximum duty cycle d max 80 85 - % soft start period t ss - 6.5 - ms boost switch rise time (23) t tr - 15 - ns boost switch fall time (23) t f - 25 - ns notes 23. guaranteed by design table 11. static and dynamic elec trical characteristics (continued) characteristics noted under conditions v in = 12 v, v out = 42 v, pwm = vdc1, m/~s = vdc1, pin & nin = vdc1, -40 c t a 105 c, pgnd = 0 v, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 41 34844a electrical ch aracteristics static and dynamic elec trical characteristics mc34844a pwm generator pwm frequency range (25) m/~s = low (slave mode) fpwm s 110 - 27000 hz pwm frequency m/~s = high (master mode) fpwm register = 768 fpwm register = 192,000 fpwm m 25000 103 27000 110 29000 112 hz pwm dimming resolution t fpwm - 0.39 - % pwm pin (direct pwm control) input pwm pin minimum pulse (25) t pwm_in 150 - - ns input pwm frequency range fpwm 110 - 27000 hz phase lock loop ck slave mode frequency lock range (24) m/~s = low (slave mode) fck s 110 - 27000 hz ck slave mode input jitter (25) m/~s = low (slave mode) fck s_jitter - - 0.1 % slave mode acquisition time m/~s = low (slave mode) fpwm s =27 khz fpwm s =110 hz t s_acq - - 50 2000 - - ms ms ck frequency (master mode) fpwm register = 768 fpwm register = 192,000 fck master 25000 103 27000 110 29000 112 hz i 2 c/sm bus physical layer [sck, sda] interface frequency range f sck 400 khz sm bus power-on-reset time t rst - 100 - ms sm bus shut down mode timeout t shutdown - 30 - ms output fall time (25) 10 f < c l < 400 f t f 40 - 160 ns output rise time (25) 10 f < c l < 400 f t r 20 - 80 ns logic output (ck) output rise and fall time c l < 100 f t r /t f - 25 - ns led channels channels rise and fall time (25) t r /t f - 23 50 ns notes 24. special considerations should be made for frequencies between 110 hz to 1.0 khz. please refer to functional device operation for further details. 25. guaranteed by design table 11. static and dynamic elec trical characteristics (continued) characteristics noted under conditions v in = 12 v, v out = 42 v, pwm = vdc1, m/~s = vdc1, pin & nin = vdc1, -40 c t a 105 c, pgnd = 0 v, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 42 freescale semiconductor 34844a functional description introduction mc34844a functional description introduction led backlighting has become very popular for small and medium lcds, due to some advantages over other backlighting schemes, such as the widely used cold cathode fluorescent lamp (ccfl). the advantages of led backlighting are low cost, long life, immunity to vibration, low operational voltage, and precise control over its intensity. however, there is an important drawback of this method. it requires more power than most of the other methods, and this is a major problem if the lcd size is large enough. to address the power consumption problem, solid state optoelectronics technologies are evolving to create brighter leds with lower power c onsumption. these new technologies together with highly efficient power management led drivers are turning leds, a more suitable solution for backlighting almost any size of lcd panel, with really conservative power consumption. one of the most common schemes for backlighting with led is the one known as ?array backlighting?. this creates a matrix of leds all over the l cd surface, using defraction and diffused layers to produce an homogenous and even light at the lcd surface. each row or column is formed by a number of leds in series, forcing a single current to flow through all leds in each string. using a current control driver, per row or column, helps the system to maintain a constant current flowing through each line, keeping a steady amount of light even with the presence of line or load variations. they can also be use as a light intensity control by increasing or decreasing the amount of current flowing through each led string. to achieve enough voltage to drive a number of leds in series, a boost converter is implemented, to produce a higher voltage from a smaller one, wh ich is typically used by the logical blocks to do their function. the 34844a implements a single channel boost converter together with 10 input channels, for driving up to 16 leds per string to create a matrix of more than 160 leds. together with its 90% efficiency and i 2 c programmable or external current control, among other features, makes the 34844a a perfect solution for backlighting small and medium size lcd panels, on low power portable and high definition devices. functional pin description input voltage supply (vin) ic power input supply voltage, is used internally to produce internal voltage regulation (vdc1, vdc3) for logic functioning, and also as an input voltage for the boost regulator. internal voltage regulator 1 (vdc1) this pin is for internal use only, and not to be used for other purposes. a capacitor of 2.2 f should be connected between this pin and ground for decoupling purposes. internal voltage regulator 2 (vdc2) this pin is for internal use only, and not to be used for other purposes. a capacitor of 2.2 f should be connected between this pin and ground for decoupling purposes. internal voltage regulator 3 (vdc3) this pin is for internal use only, and not to be used for other purposes. a capacitor of 2.2 f should be connected between this pin and ground for decoupling purposes. a 1.0 k resistor between the vdc3 and vdc1 pin is recommended for <-20 c operation. boost compensation pin (comp) passive terminal used to comp ensate the boost converter. add a capacitor and a resistor in series to gnd to stabilize the system. ic enable (en) the active high enable terminal is internally pulled high through pull-up resistors. applying 0v to this terminal would stop the ic from working. input/output clock signal (ck) this terminal can be used as an output clock signal (master mode), or input clock signal (slave mode), to synchronize more than one device. master/slave mode selection (m/~s) setting this pin high puts the device into master mode, producing an output synchronization clock at the ck terminal. setting this pin low, puts the device in slave mode, using the ck pin as an input clock. external pwm input (pwm) this terminal is internally pulled down. an external pwm signal can be applied to modulate the led channel directly in absence of an i 2 c interface. clock i 2 c signal (sck) clock line for i 2 c communication. address i 2 c signal (sda) address line for i 2 c communication.
analog integrated circuit device data freescale semiconductor 43 34844a functional description functional pin description mc34844a a0/sen address select, device select pin, or hardware over- voltage protection (ovp) control. current set (iset) each led string can drive up to 50 ma. the maximum current can be set by using a resistor from this pin to gnd. positive current scaling (pin) positive current scaling factor for the external analog current control. applying 0 v to this pin, scales the current to near 0%, and in the same way, applying v set (2.048 v typ.), the scale factor is 100%. by applying a voltage higher than 2.2 v, the scaling factor is disabled, and the internal pull-ups are activated. if pin pin and nin pin are used at the same time then by applying 0 v to the pin pin and v set to nin pin, scales the current to near 0%, and in the same way, applying v set to the pin pin and 0 v to nin pin, scales the current to 100%. by applying a voltage higher than 2.2 v, the scaling factor is disabled and the internal pull-ups are activated in both pins. negative current scaling (nin) negative current scaling factor for the external analog current control. setting 0 v to this pin scales the current to 100%, in the same way, setting v set (2.048 v typ.) the scale factor is near 0%. by applying a voltage higher than 2.2 v, the scaling factor is disabled and the internal pull-ups are activated. if pin pin and nin pin are used at the same time then by applying 0 v to the pin pin and v set to nin pin, scales the current to near 0%, and in the same way, applying v set to the pin pin and 0 v to nin pin, scales the current to 100%. by applying a voltage higher than 2.2 v, the scaling factor is disabled and the internal pull-ups are activated in both pins. ground (gnd) ground reference for all internal circuits other than the boost fet. the exposed pad (ep) should be used for thermal heat dissipation. i0-i9 current led driver, each line has the capability of driving up to 50 ma. fault detection pin (fail) when a fault situation is detect ed, this pin goes into high impedance. boost slope compensation setting resistor (slope) the resistor to be used for the slope depends on the input and output volt age difference as well as the inductor value. please use the formula shown in the components calculation section to calculate the value accordingly. power ground terminals (pgnda, pgndb) ground terminal for the internal boost fet. output voltage sense terminal (vout) input terminal to monitor the output voltage. it also supplies the input voltage for the internal regulator 2 (vdc2). switching node terminals (swa, swb) switching node of boost converter.
analog integrated circuit device data 44 freescale semiconductor 34844a functional description functional internal block description mc34844a functional internal block description figure 25. functional internal block diagram regulators the 34844a is designed to operate from input voltages in the 7.0 to 28 v range. this is stepped down internally by ldos to 2.5 v (vdc1 and vdc3) and 6 v (vdc3) for powering internal circuitry. if the input voltage falls below the uvlo threshold, the device au tomatically enters in shut down mode. power up sequence: the power up sequence for applying v in , with respect to the enable and pwm signals, is very important to assure a good performance of the part. it is recommended to follow this sequence: 1. apply v in first 2. wait for a couple of milliseconds (~2.0 ms) to let the logic and internal regulators get settled 3. take the en pin high, or keep it low depending on the operating mode 4. apply the pwm signal operating modes: the device can be operated by the en pin and/or sda/ sck bus lines, resulting in three distinct operation modes: ? manual mode, there is no i 2 c capability, the bus line pins must be tied low, and the en pin controls the on/off operation. to shutdown the pa rt in manual mode, first the pwm pin should be taken low followed by the en pin. the part will not shut down unless v out collapses to a voltage below 30 v. ? sm bus mode, en pin must be tied low and the device is turned on by any activity on the bus lines. the part shuts down if the bus lines are held low for more than 30 ms, the 30 ms watchdog timer can be disabled by i 2 c (setting seti2c bit high) or tying the en pin high. in sleep mode (en bit=0) the device reduces the power consumption by leaving ?alive? only the blocks required for i 2 c communication.to shutdown the part in sm bus mode, the en bit should first be a '0', then the sck and sda should be taken low. ?i 2 c mode, has to be configured by i 2 c communication (seti2c bit = 1) right after the ic is turned on, it prevents the part from being turned on/off by the bus. sleep mode is also present and it is intended to save power, but still keep the ic prepared to communicate by i 2 c. by taking the en bit low and then the en pin low, the part enters into a shutdown mode. mc34844 - functional block diagram regulator / power down protection / failure detection led channels led channels logic control regulators / power down 3 internal regulators protection / failure detection logic control serial interface control boost boost optical and temperature control pwm dimming over-temperature protection led open protection over-current protection under-voltage protection over-voltage protection
analog integrated circuit device data freescale semiconductor 45 34844a functional description functional internal block description mc34844a boost the integrated boost converter operates in non- synchronous mode and integrates a 2.5 a fet. an integrated sense circuit is used to sense the voltage at the led current mirror inputs and automatically sets the boost output voltage (dhc) to the minimum voltage needed to keep all leds biased with the required curr ent. the dhc is designed to operate for pulse widths > 400 ns in the led drivers. if the pulse widths are shorter than specified, the dhc circuit will not operate and the voltage across the led drivers will increase to a value given by the ovp minus the total led voltage in the led stri ng. therefore it is imperative to select the proper ovp level to minimize power dissipation. the user can program the boost frequency by i 2 c (bst[1:0]) only after the ic is powered up and before the boost circuit is turned on for the first time (pwm pin low to high). this sequence avoids boost frequency to be changed inadvertently during o peration. the first i 2 c command has to wait for 5.0 ms after the part is turned on, in order to allow sufficient time for the device power up sequence to be completed. please follow this sequence in order to change the boost frequency thru i2c: 1. take pwm pin low 2. disable the part by software (en bit = low) 3. write the new boost frequency data (bst[1:0]) 4. enable the part by software (en bit = high) 5. reconfigure all registers 6. take pwm pin high the boost controller has an integral track and hold amplifier with indefinite hold time capability, to enable immediate led on cycles after extended off times. during extended off times, the external leds cool down from their normal quiescent operating temperature and thereby experience a forward voltage cha nge, typically an increase in the forward voltage. this change can be significant for applications with a large number of series leds in a string operating at high current. if the boost controller did not track this increased change, the pot ential on the led drivers would saturate for a few cycles once the led channels are re- enabled. hardware and software ovp : the ovp value should be set to a higher value than the maximum led voltage over the whole temperature range. a good practice is to set it 5.0 v or so above the max led voltage. the ovp can be set from 11 to 62 v, ~4.0 v spaced, using the i 2 c interface (ovp register). if the i 2 c capability is not present, the ovp can be controlled either by a resistor divider connected from vout to gnd, wi th its mid point tied to the a0/sen pin, or by a zener diode from vout to the a0/sen pin (threshold = 6.5 v). during an ovp cond ition, the output voltage will go to the ovp level, which is programmed via the i 2 c interface or settled by a resistor divider on a0/sen pin, or by a zener diode. the formulas to calculate the hardware ovp using any of the two methods are as follows: table 12. operation current consumption modes mode en pin sck/sda pins i 2 c bit command current consumption mode comments manual low low n/a shutdown pwm pin = low high low n/a operational sm bus low low (> 27 ms) en bit = 0 shutdown low active en bit = 0 sleep low active en bit = 1 operational i 2 c low x seti2c bit = 1 i 2 c low power (shutdown) part doesn?t wake-up clri2c bit = 0 en bit = 0 high x seti2c bit = 1 sleep clri2c bit = 0 en bit = 0 high x seti2c bit = 1 operational clri2c bit = 0 en bit = 1 v out method 1 method 2 a0/sen a0/sen ovp = v zener2 + 6.5 v ovp = 6.5 v [(r upper / r lower ) + 1] + (100e-6 x r upper ) r upper r lower v zener2 v out
analog integrated circuit device data 46 freescale semiconductor 34844a functional description functional internal block description mc34844a over-current protection (ocp) the boost converter also features internal over-current protection (ocp) and has a user programmable over- voltage protection (ovp). the ocp operates on a cycle by cycle basis. however, if the ocp condition remains for more than 10ms then the device turns off the led drivers, the boost goes to sleep mode and the output fault pin goes into high-impedance. the device can only be restarted by recycling the enable or creating a power on reset (por). current mirror the programmable current mirr or matches the current in 10 led strings to within 2%. the maximum current is set using a resistor to gnd from t he iset pin. this can be scaled down using the i 2 c interface to 255 levels. zero current is achieved by turning off the led driver by i 2 c (registers chenx = 0h) for a duty cycle from 0% to 99%, or by pulling pwm pin low regardless of the duty cycle. i 2 c capability allows the channels to be controlled individually or in parallel. current on led channel (pin and nin mode disabled) eqn. 6 default ich[regi stervalue]=255 in the off state, the leds current is set to 0 and the boost converter stops switching. this feature allows to drive more than 80 ma of current by connecting the led string to 2 or more led channels in parallel. for example; if the application requires to drive a channels at 160 ma, then the bottom of each led string should be connected to two channels in order to duplicate the current capability (example: ch0+ch1 = 160 ma). pwm generator the pwm generator can operate in either master or slave modes, as set by the m/~s pin. in master mode, the internal pwm generator frequency is programmed through the i 2 c interface (registers fpwm). the default programmed value set the number of 27 khz clocks (40 s) in one pwm cycle. the 18-bit resolution allows minimum pwm frequencies of 110 hz to be programmed. the resulting frequency is output on the ck pin. pwm frequency eqn. 7 in slave mode, the ck pin acts as an input. the internal digital pll uses this frequency as the pwm frequency. by setting one device as master , and connecting the ck output to the input on a number of slave configured devices, all pwm frequencies are synchronized together. the duty cycle of the pwm wa veform in both master and slave modes is set using a second register on the i 2 c interface (register dpwm), an d can be controlled from 100% duty cycle to 1/256 tpwm = 0.39%. zero percent of duty cycle is achieved by turning led drivers off (register chenx = 0h) or pulling pwm pin low. an external pwm can also be used. the pwm input is 'and'ed with the internal signal. by setting the serial interface to 100% duty cycle (default), the external pin has full control of the pwm duty cycle. this pin can also be used to modulate the led at a lower frequency than the pwm dimming frequency (dhc minimum pulse width = 400 ns). power off and power on led channels the 34844a allows the user to power off and power on any channel independently thru i2c/sm-bus mode. the power on function reconnects the led driver and the feedback circuit to the channel to allow functionality to that channel again. on an opposite way when the channel is power off, the led driver and feedback circuit are disconnected to the channels. this function is very useful for applications where one or more channel has to be shutdown to avoid the output voltages goes to ovp during the start up of the part. the sequence to make these functions work is the following: to power on led channels: 1. take pwm pin low 2. set power on bit high (msb of register 09) 3. set high all channels that should be power on by writing ?1? on chenx bits (registers 08 & 09) 4. clear power on bit 5. take pwm pin high to power off led channels: 1. take pwm pin low 2. set power off bit high (msb of register 08) 3. clear all channels that should be power off by writing ?0? on chenx bits (registers 08 & 09) 4. clear power off bit 5. take pwm pin high power on bit and power off bit shouldn?t be set at the same time in order to avoid damage to the part. power on/off channels should be reconfigured every time the part gets recovered from a por or shutdown condition. this also apply if th e part is reenabled by software. if the part is reenabled by software, it is recommended to take pwm pin low, reenable the part and then follow the corresponding sequence shown above. isink a [] vset v [] 136 riset [] -------------------------------------------- ich registervalue [] 255 ----------------------------------------------------------- = fpwm hz [] 20.736mhz fpwm registervalue [] ------------------------------------------------------------------- - =
analog integrated circuit device data freescale semiconductor 47 34844a functional description functional internal block description mc34844a disabling led channels the 34844a allows the user to enable and disable each of the 10 channels separately by writing the corresponding chenx bit on registers 08 and 09 thru i2c. since the enable and disable functions reconnects the feedback circuit of the led drivers, this shouldn?t be used on any channel that shuts down either because an open led channel condition or becaus e is was previously power off. this could cause instabili ty issues since the voltage on this open led driver is not substantially above the dhc regulation voltage (0.75 v typ) and may interfere with the operation of the dynamic headroom control (dhc) which can lead to erratic output voltage regulation fail pin if a led fails open in any of th e led strings, the voltage in that particular led channel will be close to ground and the led open failure is detected. when this happens, a failure is registered, the fail pin is se t to its high-impedance stage, and the channel is shut down. the fail pin cannot be cleared for manual mode unless a complete power on reset is applied. however for i 2 c/smbus mode, the fail pin can be cleared by cycling the clear fail bit (clrfail bit = 0 - 1 - 0). this allows the user to waive any known failure and set the device for being able to detect any other failure during operation. if the fail pin cannot be cleared by software then it indicates that the failure is because of an over-current in the boost. since this is a critical failure the only way to clear it is by releasing the part from the ov er-current condition and then shutdown the part (refer to table 12 ) if i 2 c communication is not presen t, fail condition should be reset by removing the failure and re-enabling the device thru the en pin. optical and temperature control loop the 34844a supports both optic al and temperature loop control. for temperature loop control, the led brightness can be adjusted depending on the tem perature of the leds. for optical loop cont rol, the 34844a supports both optical closed loop backlight control, where the brightness of the backlight is maintained at a required level by adjusting the light output, until the desir ed level is achieved, or with ambient light control, wher e the backlight brightness increases as ambient light increases. both temperature and optical loops are supported through the pin and nin pins. each pin supports a 0 v to v set (2.048 v typ.) input range which affects the current through the leds. the pin pin increases current as the voltage rises from 0 to v set . the nin pin reduces current as the voltage rises from 0 - v set . a 6.98 kohm resistor or higher value must be used at the iset pin if the part is configured to use pin+nin control loop functionality, the 80 ma maximum current is achieved at the higher allowed level of pin/nin pins, ensuring the maximum current of the led drivers are not exceeded. the optical and temperature control loop can be disabled by i 2 c setting bits (pinen & ninen), or by tying pin and nin pins high (>2.2 v). the led driver maximum current is set to 80 ma by using a 3.48 kohm resistor at the iset pin. current on led channel (pin mode) eqn. 8 current on led channel (nin mode) eqn. 9 current on led channel (pin+nin mode) eqn. 10 vpin and vnin is the voltage applied on pin and nin pins correspondingly. for isink formula please refer to equation 1 . led failure protection open led protection if led fails open in any of the led strings, the voltage in that channel will be pulled close to zero, which will cause the channel to be disabled. as a result, the boost output voltage will go to the ovp level and then come down to the regulation level to continue powering th e rest of the led strings. short led protection if an led shorted in any of t he led strings, the device will continue to operate without interruption. however, if the shorted led happens to be in the led string with the highest forward voltage, the dhc circui t will automatically regulate the output voltage with res pect to the new highest led voltage. if more leds are shor ted in the same led string, it may cause excessive power dissipation in the channel which may cause the ott circuit to trip which will completely shutdown the device. over-temperature protection the 34844a has an on-chip te mperature sensor that measures die temperature. if the ic temperature exceeds the ott threshold, the ic will turn off all power sources inside the ic (led drivers, boost and internal regulators) until the temperature falls below the fa lling ott threshold. once it comes back on, it will operate with the default configuration (refer to table 14 ). serial interface control the 34844a uses an i 2 c interface capable of operating in standard (100 khz) or fast (400 khz) modes. the a0/sen pin can be used an address select pin to allow more than 2 devices in the system. the a0/sen pin should be held low on all chips expect the one to be addressed, where it is taken high. idim a [] isink a [] vpin v [] 2 ------------------------ = idim a [] isink a [] vset vnin ? () v [] 2 ---------------------------------------------------- = idim a [] isink a [] vset vpin vnin ? + () v [] 2 -------------------------------------------------------------------------- =
analog integrated circuit device data 48 freescale semiconductor 34844a functional device operation operational modes mc34844a functional device operation operational modes normal mode in normal operation the 34844a is programed via i 2 c to drive up to 50 ma of current through each one of the led channels. the 34844a can be configured in master or slave mode as set by the m/~s pin. in master mode , the internal pwm generator frequency is programmed through the i 2 c interface. the programmed value sets the number of 27 khz clocks (37 s) in one pwm cycle. the 18-bit resolution allows minimum pwm frequencies of 110 hz to be programmed. the resulting frequency is output on the ck pin. in slave mode, the ck pin acts as an input. the internal digital pll uses this frequency as the pwm frequency. by setting one device as a master, and connecting the ck output to the input on a number of slave configured devices, all pwm frequencies are synchronized together. for this application a0/sen pin indicates which device is enable for i 2 c control. in slave mode , an internal phase lock loop will lock the internal pwm generator period to the period of the signal present at the ck pin. the pll can lock to any frequency from 110 hz to 27 khz provided the jitter is below 1000 ppm. at frequencies above 1.0 khz, the pll will maintain lock regardless of the transient po wer conditions imposed by the user (i.e. going from 0% duty cycle to 100% at 20w led display power). below 1.0 khz, thermal time constants on the die are such that the pll may momentarily lose lock if the die temperature changes s ubstantially during a large load power step. as explained below, this anomaly can be avoided by controlling the rate of change in pw m duty cycle. to better understand this issue, consider that the on chip pll uses a vco that is subjec t to thermal drift on the order of 1000 ppm/c. further consider that the thermal time constant of the chip is on the order of single digit milliseconds. therefor e, if a large power load step is imposed by the user (i.e. going from 0% duty cycle to 100% duty cycle with a load power of 20 w), the die will experience a large temperature wave gradient t hat will propagate across the chip surface and thereby affect the instantaneous frequency of the vco. as long as such changes are within the bandwidth of the pll, the pll will be able to track and maintain lock. exceeding this rate of change may cause the pll to lose lock and the backlight will momentarily be blanked until lock is reacquired. at 110 hz lock, the pll has a bandwidth of approximately 10 hz. this means that temperature changes on the order of 100 ms are tolerable without losing lock. but full load power changes on the order of 10 ms (i.e. 110 hz pwm) are not tracked out and the pll can momentarily lose lock. if this happens, as stated above, the led drivers are momentarily disabled until lock is reacquired. this will be manifested as a perceivable short flash on the backlight immediately after the load change. to avoid this problem, one can simply limit large instantaneous changes in die temperature by invoking only small power steps when raising or lowering the display power at low pwm frequencies. for example, to maintain lock while transitioning from 0% to 100% duty cycle at 20 w load power and a pwm frequency of 110 hz would entail stepping the power at a rate not to exceed 1% per 10 ms. if a load of less than 20 w is used, then the rate of rise can be increased. as the locked pwm frequency increases (i.e. use 600 hz instead of 110 hz), the step rate can be further increased to approximately 4% per 2.0 ms. the exact step rate to avoid loss of pll lock is a function of essentially three things: (a) the composite thermal resistance of the user's pcb assembly, (b) the load power, and (c) the pwm frequency. for all cases below 1.0 khz, simply using a rate of 1% duty cycle change per pwm period will be adequate. if this is too slow, the value can be optimized experimentally once the hardware design is complete. at pwm rates above 1.0 khz, it is not necessary to control the rate of change in pwm duty cycle. it is important to point out that when operating in the master mode, one does not need to concern themselves with loss of lock since the reference clock and the vco clock are collocated on the die, and th erefore experience the same thermal shift. hence in master mode, once lock is initially acquired, it is not lost and no blanking of the display occurs. the duty cycle of th e pwm in both master and slave mode is set using a second register on the i 2 c interface. an external pwm signal can also be applied in the pwm pin. this pin is and?ed with the internal signal, giving the ability to control the du ty cycle either via i 2 c or externally by setting any of the 2 signals to 100% duty cycle. manual mode the 34844a can also be used in manual mode without using the i 2 c interface. by setting the pin m/~s high, the led dimming will be controlled by the external pwm signal. the over-voltage protection limit c an be settled by a resistor divider or a zener diode on a0/sen pin. during manual mode, all internal registers are in default configuration, refer table 14 , under this configuration the pin and nin pins are enabled to scale the current capability per string and may be disable by setting 2.2 v in the corresponding terminal. also in this mode, the device can be enabled as follows: ? en pin + pwm signal (two signals): in this configuration, the pwm signal applied to pwm pin will be in charge of controlling the led dimming and a second signal will enable or disable the chip through the en pin. ? pwm signal tied to sda pin (just one signal): in this configuration the pwm pin should be tied to the sda pin. the pwm signal applied to pwm pin will be in
analog integrated circuit device data freescale semiconductor 49 34844a functional device operation i2c bus specification mc34844a charge of controlling led dimming and enabling the device every time the pwm is active. for this configuration the en pin should be low. i2c bus specification the 34844a is a unidirectional device that can only be written by an external control unit. since the device is a 7 bit address device (1110110), the control unit needs to follow a sp ecific data transfer format which is shown in table 26 . figure 26. a complete data transfer for a complete data transfer, please use this format in the following order: 1. start condition 2. 34844a device address and write instruction (r/w = 0) 3. first data pack, it corresponds to the 34844a register that needs to be written. (refer to table 13 ) 4. second data pack, it corresponds to the value that should be written to that register. (refer to table 13 ) 5. stop condition i 2 c variables description: ? start: this condition occurs when sda changes from high to low while sck is high. ? acknowledge: the acknowledge clock pulse is generated by the master (control unit). ? the transmitter releases the sda line (high) during the acknowledge clock pulse.the receiver (34844a) must pull down the sda line during this acknowledge pulse to indicate that the data was correctly written. ? bits in the first byte: the firs t seven bits of the first bite make up the slave address. the eighth bit is the lsb (least significant bit), which dete rmines the direction of the message (write = 0) for the 34844a device, when an address is sent, each of the devices in a system compares the first seven bits after the start condition with its ad dress. if they match, the device considers itself addre ssed by the control unit as a slave-receiver. ? stop: this condition occurs when sda changes from low to high while sck is high for more inform ation about ?i 2 c bus specification? please refer to the following link: http://www.nxp.com/acrob at_download/literature/ 9398/39340011.pdf
analog integrated circuit device data 50 freescale semiconductor 34844a functional device operation logic commands and registers mc34844a logic commands and registers all registers and power on/off channels should be reconfigured every time the pa rt gets recovered from a por or shutdown condition. the configuration sequence every time the part is power up should be as follows: 1. take the pwm pin low 2. power up the part 3. configure all registers 4. take the pwm pin high for configuring the part once in operation it is recommended to follow this sequence: 1. take the pwm pin low 2. configure the registers 3. take the pwm pin high special considerations should be taken for re-configuring power on/off functions, please refer to the power off and power on led channels section. table 13. write registers reg / db d7 d6 d5 d4 d3 d2 d1 d0 00 ovp3 ovp2 ovp1 ovp0 ninen pinen en 01 clri2c seti2c 04 fpwm5 fpwm4 fpwm3 fpwm2 fpwm1 fpwm0 05 fpwm11 fpwm10 fpwm9 fpwm8 fpwm7 fpwm6 06 fpwm17 fpwm16 fpwm15 fpwm14 fpwm13 fpwm12 07 dpwm7 dpwm6 dpwm5 dpwm4 dpwm3 dpwm2 dpwm1 dpwm0 08 pwr_off chen4 chen3 chen2 chen1 chen0 09 pwr_on clrfail all_off chen9 chen8 chen7 chen6 chen5 14 bst1 bst0 f0 ich0_7 ich0_6 ich0_5 ich0_4 ich0_3 ich0_2 ich0_1 ich0_0 f1 ich1_7 ich1_6 ich1_5 ich1_4 ich1_3 ich1_2 ich1_1 ich1_0 f2 ich2_7 ich2_6 ich2_5 ich2_4 ich2_3 ich2_2 ich2_1 ich2_0 f3 ich3_7 ich3_6 ich3_5 ich3_4 ichg_3 ich3_2 ich3_1 ich3_0 f4 ich4_7 ich4_6 ich4_5 ich4_4 ich4_3 ich4_2 ich4_1 ich4_0 f5 ich5_7 ich5_6 ich5_5 ich5_4 ich5_3 ich5_2 ich5_1 ich5_0 f6 ich6_7 ich6_6 ich6_5 ich6_4 ich6_3 ich6_2 ich6_1 ich6_0 f7 ich7_7 ich7_6 ich7_5 ich7_4 ich7_3 ich7_2 ich7_1 ich7_0 f8 ich8_7 ich8_6 ich8_5 ich8_4 ich8_3 ich8_2 ich8_1 ich8_0 f9 ich9_7 ich9_6 ich9_5 ich9_4 ich9_3 ich9_2 ich9_1 ich9_0 fa ichg_7 ichg_6 ichg_5 ichg_4 ichg_3 ichg_2 ichg_1 ichg_0 table 14. register description register name default value (hex) description en 1 chip enable by software. pinen 1 pin pin enable (0=off, 1 =on) ninen 1 nin pin enable (0=off, 1 =on) ovp[3:0] f ovp voltage seti2c 0 set i 2 c communication (disable sm bus mode) clri2c 0 clear set i 2 c
analog integrated circuit device data freescale semiconductor 51 34844a functional device operation logic commands and registers mc34844a fpwm[17:0] 300 pwm frequency dpwm[7:0] ff pwm duty cycle (ffh =100%) chen[9:0] 3ff channel enable (0=off, 1=on) all_off 0 all 10 channels off at the same. in order to reactivate channels this bit should be clear. clrfail 0 clear fail if channels are re-enable. pwr_off 0 power off led channels (0=disable, 1=enable) pwr_on 0 power on led channels (0=disable, 1=enable) bst[1:0] 2 boost frequency (160,320,650,1300 khz) [0h=160 hz] ich#[7:0] ff channel current program (ffh = maximum current) ichg[7:0] ff global current program table 15. over-voltage protection register (hex) ovp value (volts) 2 11 3 15 4 19 5 23 6 27 7 31 8 35 9 39 a 43 b 47 c 51 d 55 e 59 f 62 table 14. register description register name default value (hex) description
analog integrated circuit device data freescale semiconductor 52 34844a typical applications mc34844a typical applications figure 27. manual mode (single wire control) conditions: v in = 24 v, v out = 47 v, load = 16s10p, i led = 60 ma, ovp = 53v, f sw = 300 khz figure 28. manual mode (two wire control) conditions: v in = 24 v, v out = 47 v, load = 16s10p, i led = 60 ma, ovp = 53v, f sw = 300 khz vin = 24v 0 0 0 vout 0 0 0 0 vdc1 vdc1 vcc 0 vout master ck led matrix (16s10p) manual mode (single wire control) output ovp = 55v 5.6k 5.6k + 47uf + 47uf 2.2uf 2.2uf 3.3k 3.3k 20k 20k 309k 309k 5.1k 5.1k + 13.8uf + 13.8uf 150k 150k 1.8nf 1.8nf u1 34844 u1 34844 vin 1 vdc1 28 comp 29 en 7 ck 24 m/~s 30 pwm 25 sck 27 sda 26 a0/sen 6 iset 19 pin 20 nin 21 swa 4 swb 3 vout 32 pgnda 5 pgndb 2 vdc2 31 fail 18 i0 8 i1 9 i2 10 i3 11 i4 12 i5 13 i6 14 i7 15 i8 16 i9 17 vdc3 23 slope 22 gnd 33 56pf 56pf clk clk d1 d1 2 1 2.2uf 2.2uf 22uh 22uh 1 2 2.2uf 2.2uf 1.0k vin = 24v 0 0 0 0 vcc vout vout 0 vdc1 vdc1 0 0 0 master ck output led matrix (16s10p) ovp = 55v manual mode (two wire control) unit control en pwm 2.2uf 2.2uf d5 d5 2 1 22uh 22uh 1 2 1.8nf 1.8nf 2.2uf 2.2uf 3.3k 3.3k 150k 150k + 13.8uf + 13.8uf u2 34844 u2 34844 vin 1 vdc1 28 comp 29 en 7 ck 24 m/~s 30 pwm 25 sck 27 sda 26 a0/sen 6 iset 19 pin 20 nin 21 swa 4 swb 3 vout 32 pgnda 5 pgndb 2 vdc2 31 fail 18 i0 8 i1 9 i2 10 i3 11 i4 12 i5 13 i6 14 i7 15 i8 16 i9 17 vdc3 23 slope 22 gnd 33 2.2uf 2.2uf 20k 20k 5.1k 5.1k 5.6k 5.6k 56pf 56pf + 47uf + 47uf 309k 309k 1.0k
analog integrated circuit device data freescale semiconductor 53 34844a typical applications mc34844a figure 29. i 2 c (master mode) conditions: v in = 24 v, v out = 47 v, load = 16s10p, i led = 60 ma, ovp = 53v, f sw = 300 khz figure 30. i 2 c (slave mode) conditions: v in = 24 v, v out = 47 v, load = 16s10p, i led = 60 ma, ovp = 53v, f sw = 300 khz sda sck a0sen_master en_master 0 0 0 vcc vout 0 vdc1 vdc1 0 0 0 vin = 24v 0 vdc1 master ck i2c mode (master mode) output iset = 60ma led matrix (16s10p) control unit * for i2c mode - seti2c bit should be set high. * for sm-bus mode - en pin should be connected to gnd or taken low by the control unit. 4.64k 4.64k 100pf 100pf 100k 100k 220pf 220pf 220pf 220pf 2.2uf 2.2uf 220pf 220pf 2.2uf 2.2uf 3.3k 3.3k 10uf 10uf 5.6k 5.6k 4.7uf 4.7uf 220pf 220pf 220pf 220pf + 30uf + 30uf 220pf 220pf u9 mc34844a u9 mc34844a vin 1 vdc1 28 comp 29 en 7 ck 24 m/~s 30 pwm 25 sck 27 sda 26 a0/sen 6 iset 19 pin 20 nin 21 swa 4 swb 3 vout 32 pgnda 5 pgndb 2 vdc2 31 fail 18 i0 8 i1 9 i2 10 i3 11 i4 12 i5 13 i6 14 i7 15 i8 16 i9 17 vdc3 23 slope 22 gnd 33 d533 d533 2 1 47uh 47uh 1 2 + 47uf + 47uf 4700pf 4700pf 220pf 220pf 220pf 220pf 2.2uf 2.2uf 220pf 220pf 220pf 220pf 1.0k en_slave sda sck a0sen_slave 0 0 0 vcc vout 0 vdc1 0 0 0 vin = 24v 0 vdc1 0 master ck i2c mode (slave mode) input iset = 60ma led matrix (16s10p) control unit * for i2c mode - seti2c bit should be set high. * for sm-bus mode - en pin should be connected to gnd or taken low by the control unit. 220pf 220pf 100pf 100pf 3.3k 3.3k 47uh 47uh 1 2 220pf 220pf 220pf 220pf 220pf 220pf 220pf 220pf 2.2uf 2.2uf 220pf 220pf + 30uf + 30uf d553 d553 2 1 5.6k 5.6k 2.2uf 2.2uf 4.7uf 4.7uf 2.2uf 2.2uf 4.64k 4.64k 4700pf 4700pf 10uf 10uf 220pf 220pf 100k 100k 220pf 220pf u11 mc34844a u11 mc34844a vin 1 vdc1 28 comp 29 en 7 ck 24 m/~s 30 pwm 25 sck 27 sda 26 a0/sen 6 iset 19 pin 20 nin 21 swa 4 swb 3 vout 32 pgnda 5 pgndb 2 vdc2 31 fail 18 i0 8 i1 9 i2 10 i3 11 i4 12 i5 13 i6 14 i7 15 i8 16 i9 17 vdc3 23 slope 22 gnd 33 220pf 220pf + 47uf + 47uf 220pf 220pf 1.0k
analog integrated circuit device data freescale semiconductor 54 34844a typical applications mc34844a figure 31. high vout application (manual mode) conditions: v in = 60 to 72v, v out = 120 v, load = 40s8p, i led = 60 ma, ovp = 125 v, f sw = 300 khz en_dly vdc2 en_dly pwm = 200hz (5v) 0 vin = 60v to 72v 0 0 0 0 vout = 120v vout 0 vdc1 vdc1 0 0 0 0 0 0 iset = 60ma led matrix (40s8p) ovp = 125v 10 10 pds3200 pds3200 1 3 2 4.64k 4.64k 220pf 220pf 220pf 220pf 220pf 220pf 0.1uf 0.1uf 3smbj5941b-tp 47v 3smbj5941b-tp 47v 2 1 18k 18k 6.8k 6.8k 27k 27k 100pf 100pf 200k 200k 270k 270k + 10uf 250v + 10uf 250v 2.2uf 2.2uf mmsz5268bt1g 82v mmsz5268bt1g 82v 2 1 10uf 100v 10uf 100v fds2572 fds2572 1 2 3 5 8 6 4 7 2.2uf 2.2uf 150uh 7447709151 150uh 7447709151 220pf 220pf 3.3nf 3.3nf + 47uf 100v + 47uf 100v 220pf 220pf + 10uf 250v + 10uf 250v + 10uf 250v + 10uf 250v 220pf 220pf 10.0k 10.0k 0.1uf 100v 0.1uf 100v mc34844a mc34844a vin 1 vdc1 28 comp 29 en 7 ck 24 m/~s 30 pwm 25 sck 27 sda 26 a0/sen 6 iset 19 pin 20 nin 21 swa 4 swb 3 vout 32 pgnda 5 pgndb 2 vdc2 31 fail 18 i0 8 i1 9 i2 10 i3 11 i4 12 i5 13 i6 14 i7 15 i8 16 i9 17 vdc3 23 slope 22 gnd 33 220pf 220pf 2.2uf 2.2uf 2.2uf 2.2uf 1uf 250v 1uf 250v 220pf 220pf 1.0k
analog integrated circuit device data freescale semiconductor 55 34844 components calculation components calculation the following formulas are intended for the calculation of all external components related with the boost converter and network compensation. in order to calculate a duty cycle, the internal losses of the mosfet and diode should be taken into consideration. the average input current depends directly to the output current when the internal switch is off. inductor for calculating the inductor we should consider the losses of the internal switch and wi nding resistance of the inductor. it is important to look for an inductor rated at least for the maximum input current. input capacitor the input capacitor should handle at least the following rms current. output capacitor for the output capacitor selection the internal current sense gain (csg) and the transconductance should be taken in consideration. the csg is the internal r sense times the current sense amplifier gain (a csa ). the output voltage ripple ( v out ) depends on the esr of the output capacitor, for a lo w output voltage ripple it is recommended to use ceramic capacitors that usually have very low esr. since ceramic capacitor are expensive, electrolytic or tantalum capacitors can be mixed with ceramic capacitors to have a cheaper solution. the output capacitor should handle at least the following rms current. network compensation since this boost converter is current controlle d, type ii compensation is needed. i order to calculate the network compensation, first we need to calculate all boost converter components. for this type of compensations we need to push out the right half plane zero to higher frequencies where it can?t affect the overall loop significantly. the crossover frequency must be set much lower than the location of the right half plane zero since our system has a fixed slope compensation set by r slope , r comp should be fixed for all configurations. c comp1 and c comp2 should be calculated as follows: d vout v d vin ? + vout v d v sw ? + -------------------------------------------- - = iin avg iout 1d ? ------------ - = l vin v sw ?iin avg rw () ? () d iin avg r f sw --------------------------------------------------------------------------------- - = iin max iin avg vin vout vin ? () 2lf sw vout ------------------------------------------------- + = irms cin vin vout vin ? () 2lf sw vout ------------------------------------------------- ?? ?? 0.3 = csg a csa r sense = cout r comp 5g m iout l 1d ? () vout csg ------------------------------------------------------------------- - = esr cout vout vout f sw l vout 1 d ? () -------------------------------------------------------------- - = irms cout iout d 1d ? ------------ - = f rhpz vout 1 d ? () 2 iout 2 l --------------------------------------- - = f cross f rhpz 5 -------------- - = r comp 5.6kohm =
analog integrated circuit device data 56 freescale semiconductor 34844 components calculation in order to improve the tran sient response of the boost, on the 34844a, a resistor divider has been implemented from the pwm pin to ground with a connection to the compensation network. this configuration should inject a 1.0 v signal to the comp pin and the thevenin-equivalent resistance of the divider is close to r comp , i.e. r comp = 6.8 k and r pcomp = 27 k for a 5.0 v pwm signal. slope compensation slope compensation can be expressed either in terms of ampers/second or as volts/se cond, through the use of the transfer resistance. the following formula express the slope compensation in terms of v/ s: in order to have this slope compensation, the following resistor should be set. variable definition d= boost duty cycle v out = output voltage v d = diode forward voltage v in = input voltage v sw = v drop of internal switch v out = output voltage ripple ratio iin avg = average input current i out = output current r=input current ratio iin max = maximum input current irms cin = rms current for input capacitor irms cout = rms current for output capacitor l= inductor r w = inductor winding dc resistance f sw = boost switching frequency csg= current sense gain = 0.2 v/a a csa = current sense amplifier gain = 9 r sense = current sense resistor = 22mohm c out = output capacitor r comp = compensation resistor g m = ota transconductance esr cout = esr of output capacitor f rhpz = right half plane zero frequency f cross = crossover frequency c comp1 = compensation capacitor c comp2 = shunt compensation capacitor v slope = slope compensation (v/ s) r slope = external resistor for slope compensation c comp1 2 f cross r comp 2 ------------------------------------------------------- - = c comp2 g m 6.28 f sw --------------------------- = pwm comp pin r pcomp r comp c comp1 c comp2 v slope vout vin ? () csg l2 --------------------------------------------------- - = where ?l? is in h r slope 33 3 10 v slope 5 ----------------------------- =
analog integrated circuit device data freescale semiconductor 57 34844 layout guidelines layout guidelines recommended stack-up the following table shows the recommended layer stack- up for the signals to have good shielding and thermal dissipation. decoupling caps it is recommended to place decoupling caps of 100 pf at the beginning and at the end of any power signal traces to filter high frequency noise. decoupling caps of 100 pf should be also placed at the end of any long trace to cancel antenna effects on it. these caps should be located as closed as possible to the point to be decoupled and the connection to gnd should be as short as possible. sm-bus/i 2 c communication and clock signals (sda, sck and ck) to avoid contamination of th ese signals by nearby high power or high frequency signals, it is a good practice to shield them with ground planes placed on adjacent layers. make sure the ground plane is uniform through the whole signal trace length. figure 32. recommended shielding for critical signals. these signals shall not run parallel to power signals or other clock signals in the same routing layer. if they have to cross or to be routed close to a power signal, it is a good practice to trace them perpendicularly or at 45 on a different layer to avoid coupling noise. switching node (swa & swb) the components associated to this node must be placed as close as possible to each other to keep the switching loop small enough so that it does not contaminate other signals. however, care must be taken to ensure the copper traces used to connect these compon ents together on this node are capable to handle the necessary current and voltage. as a reference, a 10 mils trace with a thickness of 1.0 oz. of copper is capable of handling one ampere. traces for connecting the induc tor, input and output caps should be as wide and short as possible to avoid adding inductance or resistance to t he loop. the placement of these components should be selected far away from sensitive signals like compensation, feedback and internal regulators to avoid power noise coupling. compensation components components related with comp pin need to be placed as close as possible to the pin. feedback signal the trace of the feedback signal (vout) should be routed perpendicularly or at 45 on a different layer to avoid coupling noise, preferably between ground or power planes. figure 33. feedback signal tracing table 16. layer stacking recommendations stack-up layer 1 (top) signal layer 2 (inner 1) ground layer 3(inner 2) signal layer 4 (bottom) ground signal ground plane ground planes signal do s s s w w w i i i t t t c c c h h h i i i n n n g g g n n n o o o d d d e e e i i i n n n p p p u u u t t t c c c a a a p p p o o o u u u t t t p p p u u u t t t c c c a a a p p p on state off state c c c o o o m m m p p p e e e n n n s s s a a a t t t i i i o o o n n n f f f e e e e e e d d d b b b a a a c c c k k k s s s i i i g g g n n n a a a l l l
analog integrated circuit device data 58 freescale semiconductor 34844 packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. ep suffix 32-pin 98asa10800d revision o
analog integrated circuit device data freescale semiconductor 59 34844 packaging package dimensions ep suffix 32-pin 98asa10800d revision o
analog integrated circuit device data 60 freescale semiconductor 34844 packaging package dimensions ep suffix 32-pin 98asa10800d revision o
analog integrated circuit device data freescale semiconductor 61 34844 revision history revision history revision date description of changes 3.0 11/2008 ? initial release 4.0 3/2009 ? added pwm pin to maximum voltages in maximum rating table. ? added disabling led channels ? rewrote fail pin section ? added i2c bus specification 5.0 5/2009 ? corrected compensation components paragraph on page 32. 6.0 9/2009 ? added part number mc34844aep/r2. 7.0 3/2010 ? combined complete data sheet for part numbers mc34844 and mc34844a to this data sheet. 8.0 7/2010 ? removed ovp=4h, ovp=3h and ovp=2h rows from table 11. ? pwm and ck frequency range changed in electrical characteristics table. 9.0 3/2012 ? added resistor between vdc1 and vdc3 on the application drawings. added to notes for vdc3 on pages 9, 14, 37, and 42.
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